Optimize vec_extract for 256/512-bit vector when index exceeds the lower 128 bits.
- vextracti32x8 $0x1, %zmm0, %ymm0 - vmovd %xmm0, %eax + valignd $8, %zmm0, %zmm0, %zmm1 + vmovd %xmm1, %eax - vextracti32x8 $0x1, %zmm0, %ymm0 - vextracti128 $0x1, %ymm0, %xmm0 - vpextrd $3, %xmm0, %eax + valignd $15, %zmm0, %zmm0, %zmm1 + vmovd %xmm1, %eax - vextractf64x2 $0x1, %ymm0, %xmm0 + valignq $2, %ymm0, %ymm0, %ymm0 - vextractf64x4 $0x1, %zmm0, %ymm0 - vextractf64x2 $0x1, %ymm0, %xmm0 - vunpckhpd %xmm0, %xmm0, %xmm0 + valignq $7, %zmm0, %zmm0, %zmm0 gcc/ChangeLog: PR target/91103 * config/i386/sse.md (*vec_extract<mode><ssescalarmodelower>_valign): New define_insn. gcc/testsuite/ChangeLog: PR target/91103 * gcc.target/i386/pr91103-1.c: New test. * gcc.target/i386/pr91103-2.c: New test.
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liuhongt
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b6db7cd41c
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60eec23b5e
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@ -233,6 +233,12 @@
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V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
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V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
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(define_mode_iterator V48_256_512_AVX512VL
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[V16SI (V8SI "TARGET_AVX512VL")
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V8DI (V4DI "TARGET_AVX512VL")
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V16SF (V8SF "TARGET_AVX512VL")
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V8DF (V4DF "TARGET_AVX512VL")])
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;; 1,2 byte AVX-512{BW,VL} vector modes. Supposed TARGET_AVX512BW baseline.
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(define_mode_iterator VI12_AVX512VL
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[V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")
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@ -828,6 +834,15 @@
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(V8HF "TI") (V16HF "OI") (V32HF "XI")
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(TI "TI")])
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(define_mode_attr sseintvecinsnmode
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[(V64QI "XI") (V32HI "XI") (V16SI "XI") (V8DI "XI") (V4TI "XI")
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(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI") (V2TI "OI")
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(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
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(V16SF "XI") (V8DF "XI")
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(V8SF "OI") (V4DF "OI")
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(V4SF "TI") (V2DF "TI")
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(TI "TI")])
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;; SSE constant -1 constraint
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(define_mode_attr sseconstm1
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[(V64QI "BC") (V32HI "BC") (V16SI "BC") (V8DI "BC") (V4TI "BC")
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@ -10517,6 +10532,23 @@
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_mode_attr vec_extract_imm_predicate
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[(V16SF "const_0_to_15_operand") (V8SF "const_0_to_7_operand")
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(V16SI "const_0_to_15_operand") (V8SI "const_0_to_7_operand")
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(V8DF "const_0_to_7_operand") (V4DF "const_0_to_3_operand")
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(V8DI "const_0_to_7_operand") (V4DI "const_0_to_3_operand")])
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(define_insn "*vec_extract<mode><ssescalarmodelower>_valign"
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[(set (match_operand:<ssescalarmode> 0 "register_operand" "=v")
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(vec_select:<ssescalarmode>
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(match_operand:V48_256_512_AVX512VL 1 "register_operand" "v")
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(parallel [(match_operand 2 "<vec_extract_imm_predicate>")])))]
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"TARGET_AVX512F
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&& INTVAL(operands[2]) >= 16 / GET_MODE_SIZE (<ssescalarmode>mode)"
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"valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}";
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecinsnmode>")])
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(define_expand "avx512f_shufps512_mask"
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[(match_operand:V16SF 0 "register_operand")
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(match_operand:V16SF 1 "register_operand")
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@ -0,0 +1,37 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512vl -O2" } */
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/* { dg-final { scan-assembler-times "valign\[dq\]" 16 } } */
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typedef float v8sf __attribute__((vector_size(32)));
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typedef float v16sf __attribute__((vector_size(64)));
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typedef int v8si __attribute__((vector_size(32)));
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typedef int v16si __attribute__((vector_size(64)));
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typedef double v4df __attribute__((vector_size(32)));
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typedef double v8df __attribute__((vector_size(64)));
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typedef long long v4di __attribute__((vector_size(32)));
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typedef long long v8di __attribute__((vector_size(64)));
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#define EXTRACT(V,S,IDX) \
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S \
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__attribute__((noipa)) \
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foo_##V##_##IDX (V v) \
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{ \
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return v[IDX]; \
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} \
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EXTRACT (v8sf, float, 4);
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EXTRACT (v8sf, float, 7);
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EXTRACT (v8si, int, 4);
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EXTRACT (v8si, int, 7);
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EXTRACT (v16sf, float, 8);
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EXTRACT (v16sf, float, 15);
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EXTRACT (v16si, int, 8);
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EXTRACT (v16si, int, 15);
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EXTRACT (v4df, double, 2);
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EXTRACT (v4df, double, 3);
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EXTRACT (v4di, long long, 2);
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EXTRACT (v4di, long long, 3);
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EXTRACT (v8df, double, 4);
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EXTRACT (v8df, double, 7);
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EXTRACT (v8di, long long, 4);
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EXTRACT (v8di, long long, 7);
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@ -0,0 +1,81 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -mavx512vl" } */
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/* { dg-require-effective-target avx512vl } */
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#define AVX512VL
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#ifndef CHECK
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#define CHECK "avx512f-helper.h"
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#endif
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#include CHECK
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#include "pr91103-1.c"
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#define RUNCHECK(U,V,S,IDX) \
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do \
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{ \
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S tmp = foo_##V##_##IDX ((V)U.x); \
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if (tmp != U.a[IDX]) \
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abort(); \
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} \
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while (0)
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void
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test_256 (void)
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{
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union512i_d di1;
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union256i_d di2;
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union512i_q q1;
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union256i_q q2;
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union512 f1;
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union256 f2;
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union512d d1;
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union256d d2;
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int sign = 1;
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int i = 0;
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for (i = 0; i < 16; i++)
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{
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di1.a[i] = 30 * (i - 30) * sign;
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f1.a[i] = 56.78 * (i - 30) * sign;
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sign = -sign;
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}
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for (i = 0; i != 8; i++)
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{
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di2.a[i] = 15 * (i + 40) * sign;
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f2.a[i] = 90.12 * (i + 40) * sign;
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q1.a[i] = 15 * (i + 40) * sign;
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d1.a[i] = 90.12 * (i + 40) * sign;
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sign = -sign;
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}
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for (i = 0; i != 4; i++)
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{
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q2.a[i] = 15 * (i + 40) * sign;
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d2.a[i] = 90.12 * (i + 40) * sign;
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sign = -sign;
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}
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RUNCHECK (f2, v8sf, float, 4);
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RUNCHECK (f2, v8sf, float, 7);
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RUNCHECK (di2, v8si, int, 4);
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RUNCHECK (di2, v8si, int, 7);
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RUNCHECK (f1, v16sf, float, 8);
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RUNCHECK (f1, v16sf, float, 15);
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RUNCHECK (di1, v16si, int, 8);
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RUNCHECK (di1, v16si, int, 15);
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RUNCHECK (d2, v4df, double, 2);
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RUNCHECK (d2, v4df, double, 3);
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RUNCHECK (q2, v4di, long long, 2);
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RUNCHECK (q2, v4di, long long, 3);
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RUNCHECK (d1, v8df, double, 4);
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RUNCHECK (d1, v8df, double, 7);
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RUNCHECK (q1, v8di, long long, 4);
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RUNCHECK (q1, v8di, long long, 7);
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}
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void
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test_128()
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{
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}
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