Remove copysign post_reload splitter for scalar modes.
It can generate better code just like avx512dq-abs-copysign-1.c shows. gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_copysign): Expand right into ANDNOT + AND + IOR, using paradoxical subregs. (ix86_split_copysign_const): Remove. (ix86_split_copysign_var): Ditto. * config/i386/i386-protos.h (ix86_split_copysign_const): Dotto. (ix86_split_copysign_var): Ditto. * config/i386/i386.md (@copysign<mode>3_const): Ditto. (@copysign<mode>3_var): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512dq-abs-copysign-1.c: Adjust testcase. * gcc.target/i386/avx512vl-abs-copysign-1.c: Adjust testcase.
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liuhongt
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60efb1fee9
@ -2115,13 +2115,9 @@ void
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ix86_expand_copysign (rtx operands[])
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{
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machine_mode mode, vmode;
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rtx dest, op0, op1, mask;
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rtx dest, op0, op1, mask, op2, op3;
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dest = operands[0];
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op0 = operands[1];
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op1 = operands[2];
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mode = GET_MODE (dest);
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mode = GET_MODE (operands[0]);
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if (mode == SFmode)
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vmode = V4SFmode;
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@ -2132,136 +2128,40 @@ ix86_expand_copysign (rtx operands[])
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else
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gcc_unreachable ();
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mask = ix86_build_signbit_mask (vmode, 0, 0);
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if (CONST_DOUBLE_P (op0))
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if (rtx_equal_p (operands[1], operands[2]))
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{
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if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
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op0 = simplify_unary_operation (ABS, mode, op0, mode);
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if (mode == SFmode || mode == DFmode)
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{
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if (op0 == CONST0_RTX (mode))
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op0 = CONST0_RTX (vmode);
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else
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{
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rtx v = ix86_build_const_vector (vmode, false, op0);
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op0 = force_reg (vmode, v);
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}
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}
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else if (op0 != CONST0_RTX (mode))
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op0 = force_reg (mode, op0);
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emit_insn (gen_copysign3_const (mode, dest, op0, op1, mask));
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}
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else
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{
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rtx nmask = ix86_build_signbit_mask (vmode, 0, 1);
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emit_insn (gen_copysign3_var
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(mode, dest, NULL_RTX, op0, op1, nmask, mask));
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}
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}
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/* Deconstruct a copysign operation into bit masks. Operand 0 is known to
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be a constant, and so has already been expanded into a vector constant. */
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void
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ix86_split_copysign_const (rtx operands[])
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{
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machine_mode mode, vmode;
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rtx dest, op0, mask, x;
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dest = operands[0];
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op0 = operands[1];
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mask = operands[3];
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mode = GET_MODE (dest);
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vmode = GET_MODE (mask);
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dest = lowpart_subreg (vmode, dest, mode);
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x = gen_rtx_AND (vmode, dest, mask);
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emit_insn (gen_rtx_SET (dest, x));
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if (op0 != CONST0_RTX (vmode))
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{
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x = gen_rtx_IOR (vmode, dest, op0);
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emit_insn (gen_rtx_SET (dest, x));
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}
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}
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/* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
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so we have to do two masks. */
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void
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ix86_split_copysign_var (rtx operands[])
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{
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machine_mode mode, vmode;
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rtx dest, scratch, op0, op1, mask, nmask, x;
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dest = operands[0];
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scratch = operands[1];
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op0 = operands[2];
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op1 = operands[3];
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nmask = operands[4];
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mask = operands[5];
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mode = GET_MODE (dest);
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vmode = GET_MODE (mask);
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if (rtx_equal_p (op0, op1))
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{
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/* Shouldn't happen often (it's useless, obviously), but when it does
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we'd generate incorrect code if we continue below. */
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emit_move_insn (dest, op0);
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emit_move_insn (operands[0], operands[1]);
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return;
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}
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if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
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dest = lowpart_subreg (vmode, operands[0], mode);
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op1 = lowpart_subreg (vmode, operands[2], mode);
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mask = ix86_build_signbit_mask (vmode, 0, 0);
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if (CONST_DOUBLE_P (operands[1]))
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{
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gcc_assert (REGNO (op1) == REGNO (scratch));
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op0 = simplify_unary_operation (ABS, mode, operands[1], mode);
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/* Optimize for 0, simplify b = copy_signf (0.0f, a) to b = mask & a. */
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if (op0 == CONST0_RTX (mode))
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{
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emit_move_insn (dest, gen_rtx_AND (vmode, mask, op1));
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return;
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}
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x = gen_rtx_AND (vmode, scratch, mask);
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emit_insn (gen_rtx_SET (scratch, x));
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dest = mask;
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op0 = lowpart_subreg (vmode, op0, mode);
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x = gen_rtx_NOT (vmode, dest);
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x = gen_rtx_AND (vmode, x, op0);
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emit_insn (gen_rtx_SET (dest, x));
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if (GET_MODE_SIZE (mode) < 16)
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op0 = ix86_build_const_vector (vmode, false, op0);
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op0 = force_reg (vmode, op0);
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}
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else
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{
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if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
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{
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x = gen_rtx_AND (vmode, scratch, mask);
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}
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else /* alternative 2,4 */
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{
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gcc_assert (REGNO (mask) == REGNO (scratch));
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op1 = lowpart_subreg (vmode, op1, mode);
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x = gen_rtx_AND (vmode, scratch, op1);
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}
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emit_insn (gen_rtx_SET (scratch, x));
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op0 = lowpart_subreg (vmode, operands[1], mode);
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if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
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{
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dest = lowpart_subreg (vmode, op0, mode);
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x = gen_rtx_AND (vmode, dest, nmask);
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}
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else /* alternative 3,4 */
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{
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gcc_assert (REGNO (nmask) == REGNO (dest));
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dest = nmask;
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op0 = lowpart_subreg (vmode, op0, mode);
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x = gen_rtx_AND (vmode, dest, op0);
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}
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emit_insn (gen_rtx_SET (dest, x));
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}
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x = gen_rtx_IOR (vmode, dest, scratch);
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emit_insn (gen_rtx_SET (dest, x));
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op2 = gen_reg_rtx (vmode);
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op3 = gen_reg_rtx (vmode);
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emit_move_insn (op2, gen_rtx_AND (vmode,
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gen_rtx_NOT (vmode, mask),
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op0));
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emit_move_insn (op3, gen_rtx_AND (vmode, mask, op1));
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emit_move_insn (dest, gen_rtx_IOR (vmode, op2, op3));
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}
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/* Expand an xorsign operation. */
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@ -135,8 +135,6 @@ extern void ix86_expand_fp_absneg_operator (enum rtx_code, machine_mode,
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extern void ix86_split_fp_absneg_operator (enum rtx_code, machine_mode,
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rtx[]);
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extern void ix86_expand_copysign (rtx []);
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extern void ix86_split_copysign_const (rtx []);
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extern void ix86_split_copysign_var (rtx []);
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extern void ix86_expand_xorsign (rtx []);
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extern bool ix86_unary_operator_ok (enum rtx_code, machine_mode, rtx[]);
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extern bool ix86_match_ccmode (rtx, machine_mode);
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@ -10861,50 +10861,6 @@
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|| (TARGET_SSE && (<MODE>mode == TFmode))"
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"ix86_expand_copysign (operands); DONE;")
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(define_insn_and_split "@copysign<mode>3_const"
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[(set (match_operand:SSEMODEF 0 "register_operand" "=Yv")
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(unspec:SSEMODEF
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[(match_operand:<ssevecmodef> 1 "nonimm_or_0_operand" "YvmC")
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(match_operand:SSEMODEF 2 "register_operand" "0")
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(match_operand:<ssevecmodef> 3 "nonimmediate_operand" "Yvm")]
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UNSPEC_COPYSIGN))]
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"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| (TARGET_SSE && (<MODE>mode == TFmode))"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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"ix86_split_copysign_const (operands); DONE;")
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(define_insn "@copysign<mode>3_var"
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[(set (match_operand:SSEMODEF 0 "register_operand" "=Yv,Yv,Yv,Yv,Yv")
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(unspec:SSEMODEF
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[(match_operand:SSEMODEF 2 "register_operand" "Yv,0,0,Yv,Yv")
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(match_operand:SSEMODEF 3 "register_operand" "1,1,Yv,1,Yv")
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(match_operand:<ssevecmodef> 4
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"nonimmediate_operand" "X,Yvm,Yvm,0,0")
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(match_operand:<ssevecmodef> 5
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"nonimmediate_operand" "0,Yvm,1,Yvm,1")]
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UNSPEC_COPYSIGN))
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(clobber (match_scratch:<ssevecmodef> 1 "=Yv,Yv,Yv,Yv,Yv"))]
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"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| (TARGET_SSE && (<MODE>mode == TFmode))"
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"#")
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(define_split
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[(set (match_operand:SSEMODEF 0 "register_operand")
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(unspec:SSEMODEF
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[(match_operand:SSEMODEF 2 "register_operand")
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(match_operand:SSEMODEF 3 "register_operand")
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(match_operand:<ssevecmodef> 4)
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(match_operand:<ssevecmodef> 5)]
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UNSPEC_COPYSIGN))
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(clobber (match_scratch:<ssevecmodef> 1))]
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"((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| (TARGET_SSE && (<MODE>mode == TFmode)))
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&& reload_completed"
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[(const_int 0)]
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"ix86_split_copysign_var (operands); DONE;")
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(define_expand "xorsign<mode>3"
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[(match_operand:MODEF 0 "register_operand")
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(match_operand:MODEF 1 "register_operand")
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@ -64,8 +64,8 @@ f6 (double x)
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}
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/* { dg-final { scan-assembler "vandps\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vorps\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vpternlogd\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vxorps\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vandpd\[^\n\r\]*xmm18" } } */
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/* { dg-final { scan-assembler "vorpd\[^\n\r\]*xmm18" } } */
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/* { dg-final { scan-assembler "vpternlogq\[^\n\r\]*xmm18" } } */
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/* { dg-final { scan-assembler "vxorpd\[^\n\r\]*xmm18" } } */
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@ -64,8 +64,8 @@ f6 (double x)
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}
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/* { dg-final { scan-assembler "vpandd\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vpord\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vpternlogd\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vpxord\[^\n\r\]*xmm16" } } */
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/* { dg-final { scan-assembler "vpandq\[^\n\r\]*xmm18" } } */
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/* { dg-final { scan-assembler "vporq\[^\n\r\]*xmm18" } } */
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/* { dg-final { scan-assembler "vpternlogq\[^\n\r\]*xmm18" } } */
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/* { dg-final { scan-assembler "vpxorq\[^\n\r\]*xmm18" } } */
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