re PR target/78900 (ICE in gcc.target/powerpc/signbit-3.c)
[gcc] 2016-12-30 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/78900 * config/rs6000/rs6000.c (rs6000_split_signbit): Change some assertions. Add support for doing the signbit if the IEEE 128-bit floating point value is in a GPR. * config/rs6000/rs6000.md (Fsignbit): Delete. (signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa". Update the length attribute if the value is in a GPR. (signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate the sign or zero extension instruction, since the value is always 0/1. (signbit<mode>2_dm2): Delete using <Fsignbit>. 2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/78953 * config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are extracting SImode to a GPR register so that we can generate a store, limit the vector to be in a traditional Altivec register for the vextuwrx instruction. [gcc/testsuite] 2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/78953 * gcc.target/powerpc/pr78953.c: New test. From-SVN: r244044
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Michael Meissner
Michael Meissner
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2016-12-30 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/78900
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* config/rs6000/rs6000.c (rs6000_split_signbit): Change some
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assertions. Add support for doing the signbit if the IEEE 128-bit
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floating point value is in a GPR.
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* config/rs6000/rs6000.md (Fsignbit): Delete.
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(signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa".
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Update the length attribute if the value is in a GPR.
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(signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate
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the sign or zero extension instruction, since the value is always
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0/1.
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(signbit<mode>2_dm2): Delete using <Fsignbit>.
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PR target/78953
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* config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are
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extracting SImode to a GPR register so that we can generate a
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store, limit the vector to be in a traditional Altivec register
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for the vextuwrx instruction.
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2017-01-03 Ian Lance Taylor <iant@google.com>
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* godump.c (go_format_type): Treat ENUMERAL_TYPE like
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@ -25170,9 +25170,7 @@ rs6000_split_signbit (rtx dest, rtx src)
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rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
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rtx shift_reg = dest_di;
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gcc_assert (REG_P (dest));
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gcc_assert (REG_P (src) || MEM_P (src));
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gcc_assert (s_mode == KFmode || s_mode == TFmode);
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gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
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if (MEM_P (src))
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{
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@ -25184,17 +25182,20 @@ rs6000_split_signbit (rtx dest, rtx src)
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else
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{
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unsigned int r = REGNO (src);
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unsigned int r = reg_or_subregno (src);
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/* If this is a VSX register, generate the special mfvsrd instruction
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to get it in a GPR. Until we support SF and DF modes, that will
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always be true. */
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gcc_assert (VSX_REGNO_P (r));
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if (INT_REGNO_P (r))
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shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
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if (s_mode == KFmode)
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emit_insn (gen_signbitkf2_dm2 (dest_di, src));
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else
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emit_insn (gen_signbittf2_dm2 (dest_di, src));
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{
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/* Generate the special mfvsrd instruction to get it in a GPR. */
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gcc_assert (VSX_REGNO_P (r));
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if (s_mode == KFmode)
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emit_insn (gen_signbitkf2_dm2 (dest_di, src));
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else
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emit_insn (gen_signbittf2_dm2 (dest_di, src));
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}
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}
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emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
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@ -518,9 +518,6 @@
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(define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
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(TF "FLOAT128_VECTOR_P (TFmode)")])
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(define_mode_attr Fsignbit [(KF "wa")
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(TF "wa")])
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; Iterator for ISA 3.0 supported floating point types
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(define_mode_iterator FP_ISA3 [SF
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DF
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@ -4744,7 +4741,7 @@
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(define_insn_and_split "signbit<mode>2_dm"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
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(unspec:SI
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[(match_operand:SIGNBIT 1 "input_operand" "<Fsignbit>,m,r")]
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[(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")]
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UNSPEC_SIGNBIT))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"#"
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@ -4754,7 +4751,24 @@
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rs6000_split_signbit (operands[0], operands[1]);
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DONE;
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}
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[(set_attr "length" "8,8,12")
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[(set_attr "length" "8,8,4")
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(set_attr "type" "mftgpr,load,integer")])
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(define_insn_and_split "*signbit<mode>2_dm_<su>ext"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
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(any_extend:DI
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(unspec:SI
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[(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")]
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UNSPEC_SIGNBIT)))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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rs6000_split_signbit (operands[0], operands[1]);
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DONE;
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}
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[(set_attr "length" "8,8,4")
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(set_attr "type" "mftgpr,load,integer")])
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;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating
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@ -4762,7 +4776,7 @@
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;; special pattern to avoid using a normal movdi.
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(define_insn "signbit<mode>2_dm2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "<Fsignbit>")
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(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa")
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(const_int 0)]
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UNSPEC_SIGNBIT))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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@ -2628,7 +2628,7 @@
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(define_insn_and_split "*vsx_extract_<mode>_store_p9"
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[(set (match_operand:<VS_scalar> 0 "memory_operand" "=Z,m")
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(vec_select:<VS_scalar>
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(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>,<VSX_EX>")
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(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>,v")
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(parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))
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(clobber (match_scratch:<VS_scalar> 3 "=<VSX_EX>,&r"))
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(clobber (match_scratch:SI 4 "=X,&r"))]
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@ -1,3 +1,8 @@
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2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/78953
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* gcc.target/powerpc/pr78953.c: New test.
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2017-01-03 Ian Lance Taylor <iant@google.com>
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* gcc.misc-tests/godump-1.c: Update for accurate representation of
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@ -0,0 +1,19 @@
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/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
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#include <altivec.h>
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/* PR 78953: mem = vec_extract (V4SI, <n>) failed if the vector was in a
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traditional FPR register. */
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void
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foo (vector int *vp, int *ip)
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{
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vector int v = *vp;
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__asm__ (" # fpr %x0" : "+d" (v));
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ip[4] = vec_extract (v, 0);
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}
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/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */
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