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5500.md (ir_vr55_store): Set latency to 0.

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* config/mips/5500.md (ir_vr55_store): Set latency to 0.
	(ir_vr55_hilo): Split into...
	(ir_vr55_mfhilo, ir_vr55_mthilo): ...these new reservations.
	(ir_vr55_imul_si, ir_vr55_imadd): Change latency to 5.
	(ir_vr55_imul_di): Change latency to 9.  Reserve vr55_mac for 4 cycles.
	Add various multiplication bypasses.
	* config/mips/mips.c (mips_rtx_costs): Adjust VR5500 costs for integer
	multiplication.

From-SVN: r81557
This commit is contained in:
Richard Sandiford 2004-05-06 09:20:44 +00:00 committed by Richard Sandiford
parent 152e35652a
commit 615ccdd358
3 changed files with 64 additions and 15 deletions
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11
gcc/ChangeLog
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@ -1,3 +1,14 @@
2004-05-06 Richard Sandiford <rsandifo@redhat.com>
* config/mips/5500.md (ir_vr55_store): Set latency to 0.
(ir_vr55_hilo): Split into...
(ir_vr55_mfhilo, ir_vr55_mthilo): ...these new reservations.
(ir_vr55_imul_si, ir_vr55_imadd): Change latency to 5.
(ir_vr55_imul_di): Change latency to 9. Reserve vr55_mac for 4 cycles.
Add various multiplication bypasses.
* config/mips/mips.c (mips_rtx_costs): Adjust VR5500 costs for integer
multiplication.
2004-05-06 Uros Bizjak <uros@kss-loka.si>
* config/i386/i386.md (*fscalexf4): Correct insn "mode"

62
gcc/config/mips/5500.md
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@ -31,7 +31,12 @@
(eq_attr "type" "load,fpload,fpidxload"))
"vr55_mem")
(define_insn_reservation "ir_vr55_store" 1
(define_bypass 4
"ir_vr55_load"
"ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd,
ir_vr55_idiv_si,ir_vr55_idiv_di")
(define_insn_reservation "ir_vr55_store" 0
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "store,fpstore,fpidxstore"))
"vr55_mem")
@ -49,32 +54,65 @@
(eq_attr "type" "xfer"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_hilo" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "mthilo,mfhilo"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_arith" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_imul_si" 3
(define_bypass 2
"ir_vr55_arith"
"ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd,
ir_vr55_idiv_si,ir_vr55_idiv_di")
(define_insn_reservation "ir_vr55_mthilo" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "mthilo"))
"vr55_mac")
(define_insn_reservation "ir_vr55_mfhilo" 5
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "mfhilo"))
"vr55_mac")
;; The default latency is for the GPR result of a mul. Bypasses handle the
;; latency of {mul,mult}->{mfhi,mflo}.
(define_insn_reservation "ir_vr55_imul_si" 5
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "imul")
(eq_attr "mode" "SI")))
"vr55_mac")
(define_insn_reservation "ir_vr55_imul_di" 4
;; The default latency is for pre-reload scheduling and handles the case
;; where a pseudo destination will be stored in a GPR (as it usually is).
;; The delay includes the latency of the dmult itself and the anticipated
;; mflo or mfhi.
;;
;; Once the mflo or mfhi has been created, bypasses handle the latency
;; between it and the dmult.
(define_insn_reservation "ir_vr55_imul_di" 9
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"vr55_mac*4")
;; The default latency is as for ir_vr55_imul_si.
(define_insn_reservation "ir_vr55_imadd" 5
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "imadd"))
"vr55_mac")
(define_insn_reservation "ir_vr55_imadd_si" 3
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "imul"))
"vr55_mac")
(define_bypass 1
"ir_vr55_imul_si,ir_vr55_imadd"
"ir_vr55_imadd"
"mips_linked_madd_p")
(define_bypass 2
"ir_vr55_imul_si,ir_vr55_imadd"
"ir_vr55_mfhilo")
(define_bypass 4
"ir_vr55_imul_di"
"ir_vr55_mfhilo")
;; Divide algorithm is early out with best latency of 7 pcycles.
;; Use worst case for scheduling purposes.

6
gcc/config/mips/mips.c
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@ -2347,9 +2347,9 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
*total = COSTS_N_INSNS (12);
else if (TUNE_MIPS3900)
*total = COSTS_N_INSNS (2);
else if (TUNE_MIPS5400 || TUNE_MIPS5500 || TUNE_SB1)
*total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
else if (TUNE_MIPS7000)
else if (TUNE_MIPS5400 || TUNE_SB1)
*total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
else if (TUNE_MIPS5500 || TUNE_MIPS7000)
*total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
else if (TUNE_MIPS9000)
*total = COSTS_N_INSNS (mode == DImode ? 8 : 3);