rs6000: Improve the load/store-with-update patterns (PR17108)
Many of these patterns only worked in 32-bit mode, and some only worked in 64-bit mode. This patch makes these use Pmode, fixing the PR. On the other hand, the stack updates have to use the same mode for the stack pointer as for the value stored, so let's simplify that a bit. Many of these patterns pass the wrong mode to avoiding_indexed_address_p (it should be the mode of the datum accessed, not the mode of the pointer). Finally, I merge some patterns into one (using iterators). PR target/17108 * config/rs6000/rs6000.c (rs6000_split_multireg_move): Adjust pattern name. (rs6000_emit_allocate_stack_1): Simplify condition. Adjust pattern name. * config/rs6000/rs6000.md (bits): Add entries for SF and DF. (*movdi_update1): Use Pmode. (movdi_<mode>_update): Fix argument to avoiding_indexed_address_p. (movdi_<mode>_update_stack): Rename to ... (movdi_update_stack): ... this. Fix comment. Change condition. Don't use Pmode. (*movsi_update1): Use Pmode. (*movsi_update2): Use Pmode. (movsi_update): Rename to ... (movsi_<mode>_update): ... this. Use Pmode. (movsi_update_stack): Fix condition. (*movhi_update1): Use Pmode. Fix argument to avoiding_indexed_address_p. (*movhi_update2): Ditto. (*movhi_update3): Ditto. (*movhi_update4): Ditto. (*movqi_update1): Ditto. (*movqi_update2): Ditto. (*movqi_update3): Ditto. (*movsf_update1, *movdf_update1): Merge, rename to... (*mov<mode>_update1): This. Use Pmode. Fix argument to avoiding_indexed_address_p. Add "size" attribute. (*movsf_update2, *movdf_update2): Merge, rename to... (*mov<mode>_update2): This. Ditto. (*movsf_update3): Use Pmode. Fix argument to avoiding_indexed_address_p. (*movsf_update4): Ditto. (allocate_stack): Simplify condition. Adjust pattern names. From-SVN: r270407
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
b39c686b82
commit
61943f94a0
@ -1,3 +1,39 @@
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2019-04-17 Segher Boessenkool <segher@kernel.crashing.org>
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PR target/17108
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* config/rs6000/rs6000.c (rs6000_split_multireg_move): Adjust pattern
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name.
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(rs6000_emit_allocate_stack_1): Simplify condition. Adjust pattern
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name.
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* config/rs6000/rs6000.md (bits): Add entries for SF and DF.
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(*movdi_update1): Use Pmode.
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(movdi_<mode>_update): Fix argument to avoiding_indexed_address_p.
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(movdi_<mode>_update_stack): Rename to ...
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(movdi_update_stack): ... this. Fix comment. Change condition. Don't
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use Pmode.
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(*movsi_update1): Use Pmode.
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(*movsi_update2): Use Pmode.
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(movsi_update): Rename to ...
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(movsi_<mode>_update): ... this. Use Pmode.
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(movsi_update_stack): Fix condition.
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(*movhi_update1): Use Pmode. Fix argument to
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avoiding_indexed_address_p.
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(*movhi_update2): Ditto.
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(*movhi_update3): Ditto.
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(*movhi_update4): Ditto.
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(*movqi_update1): Ditto.
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(*movqi_update2): Ditto.
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(*movqi_update3): Ditto.
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(*movsf_update1, *movdf_update1): Merge, rename to...
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(*mov<mode>_update1): This. Use Pmode. Fix argument to
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avoiding_indexed_address_p. Add "size" attribute.
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(*movsf_update2, *movdf_update2): Merge, rename to...
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(*mov<mode>_update2): This. Ditto.
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(*movsf_update3): Use Pmode. Fix argument to
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avoiding_indexed_address_p.
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(*movsf_update4): Ditto.
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(allocate_stack): Simplify condition. Adjust pattern names.
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2019-04-17 Jakub Jelinek <jakub@redhat.com>
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PR target/89093
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@ -24010,7 +24010,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
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emit_insn (TARGET_32BIT
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? (TARGET_POWERPC64
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? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
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: gen_movsi_update (breg, breg, delta_rtx, nsrc))
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: gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
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: gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
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used_update = true;
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}
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@ -25486,16 +25486,16 @@ rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
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size_rtx = tmp_reg;
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}
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if (Pmode == SImode)
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if (TARGET_32BIT)
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insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
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stack_pointer_rtx,
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size_rtx,
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orig_sp));
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else
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insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
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stack_pointer_rtx,
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size_rtx,
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orig_sp));
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insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
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stack_pointer_rtx,
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size_rtx,
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orig_sp));
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rtx par = PATTERN (insn);
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gcc_assert (GET_CODE (par) == PARALLEL);
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rtx set = XVECEXP (par, 0, 0);
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@ -563,7 +563,8 @@
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(TI "q")])
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;; How many bits in this mode?
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(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
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(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")
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(SF "32") (DF "64")])
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; DImode bits
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(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
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@ -9083,13 +9084,13 @@
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(define_insn "*movdi_update1"
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[(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
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(mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
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(match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
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(set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
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(plus:DI (match_dup 1) (match_dup 2)))]
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(mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_POWERPC64 && TARGET_UPDATE
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&& (!avoiding_indexed_address_p (DImode)
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|| !gpc_reg_operand (operands[2], DImode))"
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|| !gpc_reg_operand (operands[2], Pmode))"
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"@
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ldux %3,%0,%2
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ldu %3,%2(%0)"
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@ -9099,12 +9100,12 @@
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(define_insn "movdi_<mode>_update"
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[(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
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(match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
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(match_operand:DI 3 "gpc_reg_operand" "r,r"))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_POWERPC64 && TARGET_UPDATE
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&& (!avoiding_indexed_address_p (Pmode)
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&& (!avoiding_indexed_address_p (DImode)
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|| !gpc_reg_operand (operands[2], Pmode)
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|| (REG_P (operands[0])
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&& REGNO (operands[0]) == STACK_POINTER_REGNUM))"
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@ -9115,15 +9116,15 @@
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(set_attr "update" "yes")
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(set_attr "indexed" "yes,no")])
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;; This pattern is only conditional on TARGET_POWERPC64, as it is
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;; This pattern is only conditional on TARGET_64BIT, as it is
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;; needed for stack allocation, even if the user passes -mno-update.
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(define_insn "movdi_<mode>_update_stack"
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[(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
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(define_insn "movdi_update_stack"
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[(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
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(match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
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(match_operand:DI 3 "gpc_reg_operand" "r,r"))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_POWERPC64"
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(set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
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(plus:DI (match_dup 1) (match_dup 2)))]
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"TARGET_64BIT"
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"@
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stdux %3,%0,%2
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stdu %3,%2(%0)"
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@ -9133,13 +9134,13 @@
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(define_insn "*movsi_update1"
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[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
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(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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(mem:SI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I"))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& (!avoiding_indexed_address_p (SImode)
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|| !gpc_reg_operand (operands[2], SImode))"
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|| !gpc_reg_operand (operands[2], Pmode))"
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"@
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lwzux %3,%0,%2
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lwzu %3,%2(%0)"
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@ -9148,12 +9149,12 @@
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(set_attr "indexed" "yes,no")])
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(define_insn "*movsi_update2"
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[(set (match_operand:DI 3 "gpc_reg_operand" "=r")
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(sign_extend:DI
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(mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
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(match_operand:DI 2 "gpc_reg_operand" "r")))))
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(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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(plus:DI (match_dup 1) (match_dup 2)))]
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[(set (match_operand:EXTSI 3 "gpc_reg_operand" "=r")
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(sign_extend:EXTSI
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(mem:SI (plus:P (match_operand:P 1 "gpc_reg_operand" "0")
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(match_operand:P 2 "gpc_reg_operand" "r")))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_POWERPC64 && !avoiding_indexed_address_p (DImode)"
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"lwaux %3,%0,%2"
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[(set_attr "type" "load")
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@ -9161,15 +9162,15 @@
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(set_attr "update" "yes")
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(set_attr "indexed" "yes")])
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(define_insn "movsi_update"
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[(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I")))
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(define_insn "movsi_<mode>_update"
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[(set (mem:SI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I")))
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(match_operand:SI 3 "gpc_reg_operand" "r,r"))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& (!avoiding_indexed_address_p (SImode)
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|| !gpc_reg_operand (operands[2], SImode)
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|| !gpc_reg_operand (operands[2], Pmode)
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|| (REG_P (operands[0])
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&& REGNO (operands[0]) == STACK_POINTER_REGNUM))"
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"@
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@ -9187,7 +9188,7 @@
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(match_operand:SI 3 "gpc_reg_operand" "r,r"))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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""
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"TARGET_32BIT"
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"@
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stwux %3,%0,%2
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stwu %3,%2(%0)"
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@ -9197,12 +9198,12 @@
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(define_insn "*movhi_update1"
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[(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
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(mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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(mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I"))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& (!avoiding_indexed_address_p (SImode)
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&& (!avoiding_indexed_address_p (HImode)
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|| !gpc_reg_operand (operands[2], SImode))"
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"@
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lhzux %3,%0,%2
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@ -9212,15 +9213,15 @@
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(set_attr "indexed" "yes,no")])
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(define_insn "*movhi_update2"
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[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
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(zero_extend:SI
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(mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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[(set (match_operand:EXTHI 3 "gpc_reg_operand" "=r,r")
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(zero_extend:EXTHI
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(mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I")))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& (!avoiding_indexed_address_p (SImode)
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|| !gpc_reg_operand (operands[2], SImode))"
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&& (!avoiding_indexed_address_p (HImode)
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|| !gpc_reg_operand (operands[2], Pmode))"
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"@
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lhzux %3,%0,%2
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lhzu %3,%2(%0)"
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@ -9229,15 +9230,15 @@
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(set_attr "indexed" "yes,no")])
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(define_insn "*movhi_update3"
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[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
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(sign_extend:SI
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(mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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[(set (match_operand:EXTHI 3 "gpc_reg_operand" "=r,r")
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(sign_extend:EXTHI
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(mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I")))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& !(avoiding_indexed_address_p (SImode)
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&& gpc_reg_operand (operands[2], SImode))"
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&& !(avoiding_indexed_address_p (HImode)
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&& gpc_reg_operand (operands[2], Pmode))"
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"@
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lhaux %3,%0,%2
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lhau %3,%2(%0)"
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@ -9247,14 +9248,14 @@
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(set_attr "indexed" "yes,no")])
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(define_insn "*movhi_update4"
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[(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I")))
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[(set (mem:HI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I")))
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(match_operand:HI 3 "gpc_reg_operand" "r,r"))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& (!avoiding_indexed_address_p (SImode)
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|| !gpc_reg_operand (operands[2], SImode))"
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&& (!avoiding_indexed_address_p (HImode)
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|| !gpc_reg_operand (operands[2], Pmode))"
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"@
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sthux %3,%0,%2
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sthu %3,%2(%0)"
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@ -9264,13 +9265,13 @@
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(define_insn "*movqi_update1"
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[(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
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(mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
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(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
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(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
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(plus:SI (match_dup 1) (match_dup 2)))]
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(mem:QI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
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(match_operand:P 2 "reg_or_short_operand" "r,I"))))
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(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
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(plus:P (match_dup 1) (match_dup 2)))]
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"TARGET_UPDATE
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&& (!avoiding_indexed_address_p (SImode)
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|| !gpc_reg_operand (operands[2], SImode))"
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&& (!avoiding_indexed_address_p (QImode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
lbzux %3,%0,%2
|
||||
lbzu %3,%2(%0)"
|
||||
@ -9279,15 +9280,15 @@
|
||||
(set_attr "indexed" "yes,no")])
|
||||
|
||||
(define_insn "*movqi_update2"
|
||||
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
|
||||
(zero_extend:SI
|
||||
(mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
[(set (match_operand:EXTQI 3 "gpc_reg_operand" "=r,r")
|
||||
(zero_extend:EXTQI
|
||||
(mem:QI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:P 2 "reg_or_short_operand" "r,I")))))
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:P (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
&& (!avoiding_indexed_address_p (QImode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
lbzux %3,%0,%2
|
||||
lbzu %3,%2(%0)"
|
||||
@ -9296,14 +9297,14 @@
|
||||
(set_attr "indexed" "yes,no")])
|
||||
|
||||
(define_insn "*movqi_update3"
|
||||
[(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
|
||||
[(set (mem:QI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:P 2 "reg_or_short_operand" "r,I")))
|
||||
(match_operand:QI 3 "gpc_reg_operand" "r,r"))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:P (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
&& (!avoiding_indexed_address_p (QImode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
stbux %3,%0,%2
|
||||
stbu %3,%2(%0)"
|
||||
@ -9311,47 +9312,49 @@
|
||||
(set_attr "update" "yes")
|
||||
(set_attr "indexed" "yes,no")])
|
||||
|
||||
(define_insn "*movsf_update1"
|
||||
[(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
|
||||
(mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
(define_insn "*mov<mode>_update1"
|
||||
[(set (match_operand:SFDF 3 "gpc_reg_operand" "=<Ff>,<Ff>")
|
||||
(mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:P 2 "reg_or_short_operand" "r,I"))))
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:P (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_HARD_FLOAT && TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
&& (!avoiding_indexed_address_p (<MODE>mode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
lfsux %3,%0,%2
|
||||
lfsu %3,%2(%0)"
|
||||
lf<Fs>ux %3,%0,%2
|
||||
lf<Fs>u %3,%2(%0)"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "update" "yes")
|
||||
(set_attr "indexed" "yes,no")])
|
||||
(set_attr "indexed" "yes,no")
|
||||
(set_attr "size" "<bits>")])
|
||||
|
||||
(define_insn "*movsf_update2"
|
||||
[(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
|
||||
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
(define_insn "*mov<mode>_update2"
|
||||
[(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:P 2 "reg_or_short_operand" "r,I")))
|
||||
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,<Ff>"))
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:P (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_HARD_FLOAT && TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
&& (!avoiding_indexed_address_p (<MODE>mode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
stfsux %3,%0,%2
|
||||
stfsu %3,%2(%0)"
|
||||
stf<Fs>ux %3,%0,%2
|
||||
stf<Fs>u %3,%2(%0)"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "update" "yes")
|
||||
(set_attr "indexed" "yes,no")])
|
||||
(set_attr "indexed" "yes,no")
|
||||
(set_attr "size" "<bits>")])
|
||||
|
||||
(define_insn "*movsf_update3"
|
||||
[(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
|
||||
(mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
(mem:SF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:P 2 "reg_or_short_operand" "r,I"))))
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:P (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_SOFT_FLOAT && TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
&& (!avoiding_indexed_address_p (SFmode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
lwzux %3,%0,%2
|
||||
lwzu %3,%2(%0)"
|
||||
@ -9360,14 +9363,14 @@
|
||||
(set_attr "indexed" "yes,no")])
|
||||
|
||||
(define_insn "*movsf_update4"
|
||||
[(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
|
||||
[(set (mem:SF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:P 2 "reg_or_short_operand" "r,I")))
|
||||
(match_operand:SF 3 "gpc_reg_operand" "r,r"))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:P (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_SOFT_FLOAT && TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
&& (!avoiding_indexed_address_p (SFmode)
|
||||
|| !gpc_reg_operand (operands[2], Pmode))"
|
||||
"@
|
||||
stwux %3,%0,%2
|
||||
stwu %3,%2(%0)"
|
||||
@ -9375,39 +9378,6 @@
|
||||
(set_attr "update" "yes")
|
||||
(set_attr "indexed" "yes,no")])
|
||||
|
||||
(define_insn "*movdf_update1"
|
||||
[(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
|
||||
(mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_HARD_FLOAT && TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
"@
|
||||
lfdux %3,%0,%2
|
||||
lfdu %3,%2(%0)"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "update" "yes")
|
||||
(set_attr "indexed" "yes,no")
|
||||
(set_attr "size" "64")])
|
||||
|
||||
(define_insn "*movdf_update2"
|
||||
[(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
|
||||
(match_operand:DF 3 "gpc_reg_operand" "d,d"))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_HARD_FLOAT && TARGET_UPDATE
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
"@
|
||||
stfdux %3,%0,%2
|
||||
stfdu %3,%2(%0)"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "update" "yes")
|
||||
(set_attr "indexed" "yes,no")])
|
||||
|
||||
|
||||
;; After inserting conditional returns we can sometimes have
|
||||
;; unnecessary register moves. Unfortunately we cannot have a
|
||||
@ -9771,14 +9741,14 @@
|
||||
emit_stack_clash_protection_probe_loop_start (&loop_lab, &end_loop,
|
||||
last_addr, rotated);
|
||||
|
||||
if (Pmode == SImode)
|
||||
if (TARGET_32BIT)
|
||||
emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
|
||||
stack_pointer_rtx,
|
||||
update, chain));
|
||||
else
|
||||
emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
|
||||
stack_pointer_rtx,
|
||||
update, chain));
|
||||
emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
|
||||
stack_pointer_rtx,
|
||||
update, chain));
|
||||
emit_stack_clash_protection_probe_loop_end (loop_lab, end_loop,
|
||||
last_addr, rotated);
|
||||
}
|
||||
@ -9802,7 +9772,7 @@
|
||||
neg_op0 = GEN_INT (-INTVAL (operands[1]));
|
||||
|
||||
insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
|
||||
: gen_movdi_di_update_stack))
|
||||
: gen_movdi_update_stack))
|
||||
(stack_pointer_rtx, stack_pointer_rtx, neg_op0,
|
||||
chain));
|
||||
/* Since we didn't use gen_frame_mem to generate the MEM, grab
|
||||
|
||||
Loading…
Reference in New Issue
Block a user