md.texi: (reduc_smin, reduc_umin, reduc_splus, reduc_uplus):
* doc/md.texi: (reduc_smin, reduc_umin, reduc_splus, reduc_uplus): (vec_shl, vec_shr): Document new operations. * tree.def (VEC_RSHIFT_EXPR, VEC_LSHIFT_EXPR): Fix comment. From-SVN: r102951
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2005-08-10 Dorit Nuzman <dorit@il.ibm.com>
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* doc/md.texi: (reduc_smin, reduc_umin, reduc_splus, reduc_uplus):
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(vec_shl, vec_shr): Document new operations.
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* tree.def (VEC_RSHIFT_EXPR, VEC_LSHIFT_EXPR): Fix comment.
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2005-08-10 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/predicates.md (indexed_or_indirect_address): New.
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@ -3039,6 +3039,43 @@ Signed minimum and maximum operations. When used with floating point,
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if both operands are zeros, or if either operand is @code{NaN}, then
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it is unspecified which of the two operands is returned as the result.
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@cindex @code{reduc_smin_@var{m}} instruction pattern
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@cindex @code{reduc_smax_@var{m}} instruction pattern
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@item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
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Find the signed minimum/maximum of the elements of a vector. The vector is
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operand 1, and the scalar result is stored in the least significant bits of
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operand 0 (also a vector). The output and input vector should have the same
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modes.
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@cindex @code{reduc_umin_@var{m}} instruction pattern
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@cindex @code{reduc_umax_@var{m}} instruction pattern
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@item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
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Find the unsigned minimum/maximum of the elements of a vector. The vector is
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operand 1, and the scalar result is stored in the least significant bits of
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operand 0 (also a vector). The output and input vector should have the same
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modes.
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@cindex @code{reduc_splus_@var{m}} instruction pattern
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@item @samp{reduc_splus_@var{m}}
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Compute the sum of the signed elements of a vector. The vector is opernad 1,
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and the scalar result is stored in the least significant bits of opernad 0
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(also a vector). The output and input vector should have the same modes.
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@cindex @code{reduc_uplus_@var{m}} instruction pattern
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@item @samp{reduc_uplus_@var{m}}
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Compute the sum of the unsigned elements of a vector. The vector is opernad 1,
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and the scalar result is stored in the least significant bits of opernad 0
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(also a vector). The output and input vector should have the same modes.
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@cindex @code{vec_shl_@var{m}} instruction pattern
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@cindex @code{vec_shr_@var{m}} instruction pattern
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@item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
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Whole vector left/right shift in bits.
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Operand 1 is a vector to be shifted.
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Operand 2 is an integer shift amount in bits.
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Operand 0 is where the resulting shifted vector is stored.
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The output and input vectors should have the same modes.
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@cindex @code{mulhisi3} instruction pattern
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@item @samp{mulhisi3}
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Multiply operands 1 and 2, which have mode @code{HImode}, and store
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@ -957,7 +957,7 @@ DEFTREECODE (REDUC_MAX_EXPR, "reduc_max_expr", tcc_unary, 1)
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DEFTREECODE (REDUC_MIN_EXPR, "reduc_min_expr", tcc_unary, 1)
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DEFTREECODE (REDUC_PLUS_EXPR, "reduc_plus_expr", tcc_unary, 1)
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/* Whole vector left/right shift in bytes.
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/* Whole vector left/right shift in bits.
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Operand 0 is a vector to be shifted.
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Operand 1 is an integer shift amount in bits. */
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DEFTREECODE (VEC_LSHIFT_EXPR, "vec_lshift_expr", tcc_binary, 2)
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