rs6000.md (fix_truncdfsi2_internal): Ignore DImode in FPR as preference.
* config/rs6000/rs6000.md (fix_truncdfsi2_internal): Ignore DImode in FPR as preference. (fctiwz): Same. (floatdidf2, fix_truncdfdi2): Same. (floatdisf2, floatditf2, fix_trunctfdi2): Same. (floatditf2): Same. (floatsitf2, fix_trunctfsi2): SImode in GPR. (ctrdi): Remove FPR alternative and splitter. From-SVN: r55212
This commit is contained in:
parent
77966be34b
commit
61c07d3c9b
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@ -1,4 +1,15 @@
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2002-07-02 Will Cohen <wcohen@redhat.com>
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2002-07-03 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.md (fix_truncdfsi2_internal): Ignore DImode
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in FPR as preference.
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(fctiwz): Same.
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(floatdidf2, fix_truncdfdi2): Same.
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(floatdisf2, floatditf2, fix_trunctfdi2): Same.
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(floatditf2): Same.
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(floatsitf2, fix_trunctfsi2): SImode in GPR.
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(ctrdi): Remove FPR alternative and splitter.
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2002-07-03 Will Cohen <wcohen@redhat.com>
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* config/i386/i386.c (x86_integer_DFmode_moves): Disable for PPro.
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@ -5486,7 +5486,7 @@
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(define_insn "*fix_truncdfsi2_internal"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=*f"))
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(clobber (match_operand:DI 3 "memory_operand" "=o"))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
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"#"
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@ -5522,7 +5522,7 @@
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; because the first makes it clear that operand 0 is not live
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; before the instruction.
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(define_insn "fctiwz"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
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(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
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"{fcirz|fctiwz} %0,%1"
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@ -5530,13 +5530,13 @@
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(define_insn "floatdidf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
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(float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
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"fcfid %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "fix_truncdfdi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
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(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
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"fctidz %0,%1"
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@ -5545,7 +5545,7 @@
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;; This only is safe if rounding mode set appropriately.
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(define_insn_and_split "floatdisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
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(float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
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(clobber (match_scratch:DF 2 "=f"))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
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"#"
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@ -8316,7 +8316,7 @@
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(define_insn_and_split "floatditf2"
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[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
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(float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
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(float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
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(clobber (match_scratch:DF 2 "=f"))]
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"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
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&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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@ -8330,7 +8330,7 @@
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(define_insn_and_split "floatsitf2"
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[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
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(float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
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(float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
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(clobber (match_scratch:DF 2 "=f"))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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@ -8342,7 +8342,7 @@
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"")
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(define_insn_and_split "fix_trunctfdi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
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(fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
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"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
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&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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@ -8355,7 +8355,7 @@
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"")
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(define_insn_and_split "fix_trunctfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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@ -13333,11 +13333,9 @@
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(plus:DI (match_dup 0)
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(const_int -1)))
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(clobber (match_scratch:CC 2 ""))
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(clobber (match_scratch:DI 3 ""))
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(clobber (match_dup 4))])]
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(clobber (match_scratch:DI 3 ""))])]
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"TARGET_POWERPC64"
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"
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{ operands[4] = gen_reg_rtx (DImode); }")
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"")
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;; We need to be able to do this for any operand, including MEM, or we
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;; will cause reload to blow up since we don't allow output reloads on
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@ -13395,16 +13393,15 @@
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(define_insn "*ctrdi_internal1"
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[(set (pc)
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(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
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(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
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(const_int 1))
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r,r"))
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(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
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(clobber (match_scratch:CC 3 "=X,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r"))]
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"TARGET_POWERPC64"
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"*
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{
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@ -13416,20 +13413,19 @@
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return \"bdz $+8\;b %l0\";
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}"
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[(set_attr "type" "branch")
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(set_attr "length" "*,12,16,24")])
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(set_attr "length" "*,12,16")])
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(define_insn "*ctrdi_internal2"
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[(set (pc)
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(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
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(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
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(const_int 1))
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(pc)
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(label_ref (match_operand 0 "" ""))))
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r,r"))
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(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
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(clobber (match_scratch:CC 3 "=X,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r"))]
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"TARGET_POWERPC64"
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"*
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{
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@ -13441,7 +13437,7 @@
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return \"{bdn|bdnz} $+8\;b %l0\";
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}"
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[(set_attr "type" "branch")
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(set_attr "length" "*,12,16,24")])
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(set_attr "length" "*,12,16")])
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;; Similar, but we can use GE since we have a REG_NONNEG.
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@ -13495,16 +13491,15 @@
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(define_insn "*ctrdi_internal3"
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[(set (pc)
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(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
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(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r,r"))
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(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
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(clobber (match_scratch:CC 3 "=X,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r"))]
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"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
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"*
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{
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@ -13516,20 +13511,19 @@
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return \"bdz $+8\;b %l0\";
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}"
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[(set_attr "type" "branch")
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(set_attr "length" "*,12,16,24")])
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(set_attr "length" "*,12,16")])
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(define_insn "*ctrdi_internal4"
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[(set (pc)
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(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
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(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
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(const_int 0))
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(pc)
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(label_ref (match_operand 0 "" ""))))
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r,r"))
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(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
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(clobber (match_scratch:CC 3 "=X,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r"))]
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"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
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"*
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{
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@ -13541,7 +13535,7 @@
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return \"{bdn|bdnz} $+8\;b %l0\";
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}"
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[(set_attr "type" "branch")
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(set_attr "length" "*,12,16,24")])
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(set_attr "length" "*,12,16")])
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;; Similar but use EQ
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@ -13595,16 +13589,15 @@
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(define_insn "*ctrdi_internal5"
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[(set (pc)
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(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
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(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
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(const_int 1))
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r,r"))
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(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
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(clobber (match_scratch:CC 3 "=X,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r"))]
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"TARGET_POWERPC64"
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"*
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{
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@ -13616,20 +13609,19 @@
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return \"{bdn|bdnz} $+8\;b %l0\";
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}"
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[(set_attr "type" "branch")
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(set_attr "length" "*,12,16,24")])
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(set_attr "length" "*,12,16")])
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(define_insn "*ctrdi_internal6"
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[(set (pc)
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(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
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(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
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(const_int 1))
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(pc)
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(label_ref (match_operand 0 "" ""))))
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
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(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r,r"))
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(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
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(clobber (match_scratch:CC 3 "=X,&x,&x"))
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(clobber (match_scratch:DI 4 "=X,X,r"))]
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"TARGET_POWERPC64"
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"*
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{
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@ -13641,7 +13633,7 @@
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return \"bdz $+8\;b %l0\";
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}"
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[(set_attr "type" "branch")
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(set_attr "length" "*,12,16,24")])
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(set_attr "length" "*,12,16")])
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;; Now the splitters if we could not allocate the CTR register
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@ -13705,15 +13697,14 @@
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(if_then_else (match_operator 2 "comparison_operator"
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[(match_operand:DI 1 "gpc_reg_operand" "")
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(const_int 1)])
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(match_operand 6 "" "")
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(match_operand 7 "" "")))
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(match_operand 5 "" "")
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(match_operand 6 "" "")))
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(set (match_operand:DI 0 "gpc_reg_operand" "")
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(plus:DI (match_dup 1)
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(const_int -1)))
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(clobber (match_scratch:CC 3 ""))
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(clobber (match_scratch:DI 4 ""))
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(clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
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"TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))"
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(clobber (match_scratch:DI 4 ""))]
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"TARGET_POWERPC64 && reload_completed"
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[(parallel [(set (match_dup 3)
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(compare:CC (plus:DI (match_dup 1)
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(const_int -1))
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@ -13721,11 +13712,11 @@
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(set (match_dup 0)
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(plus:DI (match_dup 1)
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(const_int -1)))])
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(set (pc) (if_then_else (match_dup 8)
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(match_dup 6)
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(match_dup 7)))]
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(set (pc) (if_then_else (match_dup 7)
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(match_dup 5)
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(match_dup 6)))]
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"
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{ operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
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{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
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const0_rtx); }")
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(define_split
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@ -13733,13 +13724,12 @@
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(if_then_else (match_operator 2 "comparison_operator"
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[(match_operand:DI 1 "gpc_reg_operand" "")
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(const_int 1)])
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(match_operand 6 "" "")
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(match_operand 7 "" "")))
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(match_operand 5 "" "")
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(match_operand 6 "" "")))
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(set (match_operand:DI 0 "nonimmediate_operand" "")
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(plus:DI (match_dup 1) (const_int -1)))
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(clobber (match_scratch:CC 3 ""))
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(clobber (match_scratch:DI 4 ""))
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(clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
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(clobber (match_scratch:DI 4 ""))]
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"TARGET_POWERPC64 && reload_completed
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&& ! gpc_reg_operand (operands[0], DImode)"
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[(parallel [(set (match_dup 3)
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|
@ -13751,51 +13741,13 @@
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(const_int -1)))])
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(set (match_dup 0)
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(match_dup 4))
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(set (pc) (if_then_else (match_dup 8)
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(match_dup 6)
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(match_dup 7)))]
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(set (pc) (if_then_else (match_dup 7)
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(match_dup 5)
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(match_dup 6)))]
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"
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{ operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
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{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
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const0_rtx); }")
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||||
|
||||
(define_split
|
||||
[(set (pc)
|
||||
(if_then_else (match_operator 2 "comparison_operator"
|
||||
[(match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(const_int 1)])
|
||||
(match_operand 6 "" "")
|
||||
(match_operand 7 "" "")))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (match_dup 1)
|
||||
(const_int -1)))
|
||||
(clobber (match_scratch:CC 3 ""))
|
||||
(clobber (match_scratch:DI 4 ""))
|
||||
(clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
|
||||
"TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))"
|
||||
[(set (match_dup 5)
|
||||
(match_dup 1))
|
||||
(set (match_dup 4)
|
||||
(match_dup 5))
|
||||
(parallel [(set (match_dup 3)
|
||||
(compare:CC (plus:DI (match_dup 4)
|
||||
(const_int -1))
|
||||
(const_int 0)))
|
||||
(set (match_dup 4)
|
||||
(plus:DI (match_dup 4)
|
||||
(const_int -1)))])
|
||||
(set (match_dup 5)
|
||||
(match_dup 4))
|
||||
(set (match_dup 0)
|
||||
(match_dup 5))
|
||||
(set (pc) (if_then_else (match_dup 8)
|
||||
(match_dup 6)
|
||||
(match_dup 7)))]
|
||||
"
|
||||
{
|
||||
operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
|
||||
const0_rtx);
|
||||
}")
|
||||
|
||||
|
||||
(define_insn "trap"
|
||||
[(trap_if (const_int 1) (const_int 0))]
|
||||
|
|
Loading…
Reference in New Issue