spe.md (SPE64): New mode macro.
* config/rs6000/spe.md (SPE64): New mode macro. (mov_sidf_e500_subreg0): Change to mov_si<mode>_e500_subreg0. Add memory load. (mov_si<mode>_e500_subreg0_2): New. (mov_sidf_e500_subreg4): Change to mov_si<mode>_e500_subreg4. Add memory load. (mov_si<mode>_e500_subreg4_2): New. * config/rs6000/predicates.md (input_operand): Do not allow invalid E500 subregs. (rs6000_nonimmediate_operand): Check for invalid E500 subregs also if TARGET_SPE. * config/rs6000/rs6000.c (invalid_e500_subreg): Check for subregs involving DFmode if TARGET_E500_DOUBLE. Check for subregs involving vector modes if TARGET_SPE. From-SVN: r119094
This commit is contained in:
Joseph Myers
Joseph Myers
parent
7c21975d47
commit
61c7623949
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@ -1,3 +1,20 @@
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2006-11-22 Joseph Myers <joseph@codesourcery.com>
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* config/rs6000/spe.md (SPE64): New mode macro.
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(mov_sidf_e500_subreg0): Change to mov_si<mode>_e500_subreg0. Add
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memory load.
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(mov_si<mode>_e500_subreg0_2): New.
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(mov_sidf_e500_subreg4): Change to mov_si<mode>_e500_subreg4. Add
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memory load.
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(mov_si<mode>_e500_subreg4_2): New.
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* config/rs6000/predicates.md (input_operand): Do not allow
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invalid E500 subregs.
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(rs6000_nonimmediate_operand): Check for invalid E500 subregs also
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if TARGET_SPE.
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* config/rs6000/rs6000.c (invalid_e500_subreg): Check for subregs
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involving DFmode if TARGET_E500_DOUBLE. Check for subregs
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involving vector modes if TARGET_SPE.
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2006-11-22 Kaz Kojima <kkojima@gcc.gnu.org>
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Revert
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@ -722,6 +722,12 @@
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&& easy_vector_constant (op, mode))
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return 1;
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/* Do not allow invalid E500 subregs. */
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if ((TARGET_E500_DOUBLE || TARGET_SPE)
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&& GET_CODE (op) == SUBREG
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&& invalid_e500_subreg (op, mode))
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return 0;
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/* For floating-point or multi-word mode, the only remaining valid type
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is a register. */
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if (SCALAR_FLOAT_MODE_P (mode)
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@ -756,7 +762,7 @@
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(define_predicate "rs6000_nonimmediate_operand"
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(match_code "reg,subreg,mem")
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{
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if (TARGET_E500_DOUBLE
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if ((TARGET_E500_DOUBLE || TARGET_SPE)
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&& GET_CODE (op) == SUBREG
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&& invalid_e500_subreg (op, mode))
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return 0;
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@ -2713,18 +2713,29 @@ build_mask64_2_operands (rtx in, rtx *out)
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bool
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invalid_e500_subreg (rtx op, enum machine_mode mode)
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{
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/* Reject (subreg:SI (reg:DF)). */
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if (GET_CODE (op) == SUBREG
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if (TARGET_E500_DOUBLE)
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{
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/* Reject (subreg:SI (reg:DF)). */
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if (GET_CODE (op) == SUBREG
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&& mode == SImode
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&& REG_P (SUBREG_REG (op))
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&& GET_MODE (SUBREG_REG (op)) == DFmode)
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return true;
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/* Reject (subreg:DF (reg:DI)). */
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if (GET_CODE (op) == SUBREG
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&& mode == DFmode
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&& REG_P (SUBREG_REG (op))
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&& GET_MODE (SUBREG_REG (op)) == DImode)
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return true;
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}
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if (TARGET_SPE
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&& GET_CODE (op) == SUBREG
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&& mode == SImode
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&& REG_P (SUBREG_REG (op))
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&& GET_MODE (SUBREG_REG (op)) == DFmode)
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return true;
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/* Reject (subreg:DF (reg:DI)). */
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if (GET_CODE (op) == SUBREG
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&& mode == DFmode
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&& REG_P (SUBREG_REG (op))
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&& GET_MODE (SUBREG_REG (op)) == DImode)
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&& SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op)))
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&& SUBREG_BYTE (op) != 4)
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return true;
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return false;
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@ -32,6 +32,9 @@
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(E500_CR_IOR_COMPARE 1012)
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])
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;; Modes using a 64-bit register.
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(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI])
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(define_insn "*negsf2_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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@ -2241,17 +2244,39 @@
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}"
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[(set_attr "length" "8,8")])
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(define_insn "*mov_sidf_e500_subreg0"
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[(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 0)
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(match_operand:SI 1 "register_operand" "r"))]
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"TARGET_E500_DOUBLE"
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"evmergelo %0,%1,%0")
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(define_insn "*mov_si<mode>_e500_subreg0"
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[(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,&r") 0)
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(match_operand:SI 1 "input_operand" "r,m"))]
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"(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)"
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"@
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evmergelo %0,%1,%0
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evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0")
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(define_insn "*mov_sidf_e500_subreg4"
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[(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 4)
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(match_operand:SI 1 "register_operand" "r"))]
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"TARGET_E500_DOUBLE"
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"mr %0,%1")
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;; ??? Could use evstwwe for memory stores in some cases, depending on
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;; the offset.
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(define_insn "*mov_si<mode>_e500_subreg0_2"
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[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
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(subreg:SI (match_operand:SPE64 1 "register_operand" "+r,&r") 0))]
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"(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)"
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"@
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evmergehi %0,%0,%1
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evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0")
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(define_insn "*mov_si<mode>_e500_subreg4"
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[(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,r") 4)
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(match_operand:SI 1 "input_operand" "r,m"))]
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"(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)"
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"@
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mr %0,%1
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{l%U1%X1|lwz%U1%X1} %0,%1")
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(define_insn "*mov_si<mode>_e500_subreg4_2"
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[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
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(subreg:SI (match_operand:SPE64 1 "register_operand" "r,r") 4))]
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"(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)"
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"@
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mr %0,%1
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{st%U0%X0|stw%U0%X0} %1,%0")
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;; FIXME: Allow r=CONST0.
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(define_insn "*movdf_e500_double"
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