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locks.h: Formatting. 

* sysdep/powerpc/locks.h: Formatting.
	(_LARX): Define.
	(_STCX): Define.
	(compare_and_swap): Use _LARX and _STCX.
	(compare_and_swap_release): Likewise.

From-SVN: r55855
This commit is contained in:
Alan Modra 2002-07-29 23:26:27 +00:00 committed by Alan Modra
parent bd11db39e8
commit 61fd68b4c3
2 changed files with 39 additions and 18 deletions
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8
libjava/ChangeLog
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@ -1,3 +1,11 @@
2002-07-27 Alan Modra <amodra@bigpond.net.au>
* sysdep/powerpc/locks.h: Formatting.
(_LARX): Define.
(_STCX): Define.
(compare_and_swap): Use _LARX and _STCX.
(compare_and_swap_release): Likewise.
2002-07-26 Tom Tromey <tromey@redhat.com>
* java/net/Authenticator.java: New version from Classpath.

49
libjava/sysdep/powerpc/locks.h
View File

@ -11,26 +11,38 @@ details. */
#ifndef __SYSDEP_LOCKS_H__
#define __SYSDEP_LOCKS_H__
#ifdef __powerpc64__
#define _LARX "ldarx "
#define _STCX "stdcx. "
#else
#define _LARX "lwarx "
#ifdef __PPC405__
#define _STCX "sync; stwcx. "
#else
#define _STCX "stwcx. "
#endif
#endif
typedef size_t obj_addr_t; /* Integer type big enough for object */
/* address. */
inline static bool
compare_and_swap(volatile obj_addr_t *addr,
obj_addr_t old,
obj_addr_t new_val)
compare_and_swap (volatile obj_addr_t *addr, obj_addr_t old,
obj_addr_t new_val)
{
int ret;
__asm__ __volatile__ (
"0: lwarx %0,0,%1 ;"
"0: " _LARX "%0,0,%1 ;"
" xor. %0,%3,%0;"
" bne 1f;"
" stwcx. %2,0,%1;"
" " _STCX "%2,0,%1;"
" bne- 0b;"
"1: "
: "=&r"(ret)
: "r"(addr), "r"(new_val), "r"(old)
: "=&r" (ret)
: "r" (addr), "r" (new_val), "r" (old)
: "cr0", "memory");
/* This version of __compare_and_swap is to be used when acquiring
a lock, so we don't need to worry about whether other memory
operations have completed, but we do need to be sure that any loads
@ -40,37 +52,38 @@ compare_and_swap(volatile obj_addr_t *addr,
}
inline static void
release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
release_set (volatile obj_addr_t *addr, obj_addr_t new_val)
{
__asm__ __volatile__ ("sync" : : : "memory");
*(addr) = new_val;
*addr = new_val;
}
inline static bool
compare_and_swap_release(volatile obj_addr_t *addr,
obj_addr_t old,
obj_addr_t new_val)
compare_and_swap_release (volatile obj_addr_t *addr, obj_addr_t old,
obj_addr_t new_val)
{
int ret;
__asm__ __volatile__ ("sync" : : : "memory");
__asm__ __volatile__ (
"0: lwarx %0,0,%1 ;"
"0: " _LARX "%0,0,%1 ;"
" xor. %0,%3,%0;"
" bne 1f;"
" stwcx. %2,0,%1;"
" " _STCX "%2,0,%1;"
" bne- 0b;"
"1: "
: "=&r"(ret)
: "r"(addr), "r"(new_val), "r"(old)
: "=&r" (ret)
: "r" (addr), "r" (new_val), "r" (old)
: "cr0", "memory");
return ret == 0;
}
// Ensure that subsequent instructions do not execute on stale
// data that was loaded from memory before the barrier.
inline static void
read_barrier()
read_barrier ()
{
__asm__ __volatile__ ("isync" : : : "memory");
}
@ -78,7 +91,7 @@ read_barrier()
// Ensure that prior stores to memory are completed with respect to other
// processors.
inline static void
write_barrier()
write_barrier ()
{
__asm__ __volatile__ ("sync" : : : "memory");
}