alpha.md: Revert Thu Nov 26 change that came in through the last gcc2 merge...

* alpha.md: Revert Thu Nov 26 change that came in through the
        last gcc2 merge: reinstate (plus (plus ...)) reload patterns.
        Avoid earlyclobber when possible.

From-SVN: r29466
This commit is contained in:
Richard Henderson 1999-09-16 16:38:51 -07:00 committed by Richard Henderson
parent a218d5ba2b
commit 626e2d6db5
2 changed files with 97 additions and 0 deletions

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@ -1,3 +1,9 @@
Thu Sep 16 16:35:41 1999 Richard Henderson <rth@cygnus.com>
* alpha.md: Revert Thu Nov 26 change that came in through the
last gcc2 merge: reinstate (plus (plus ...)) reload patterns.
Avoid earlyclobber when possible.
Thu Sep 16 18:44:48 1999 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* libgcc2.c (__do_global_ctors): Call atexit with one arg.

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@ -650,6 +650,97 @@
s%2addq %1,%3,%0
s%2subq %1,%n3,%0")
;; These variants of the above insns can occur if the third operand
;; is the frame pointer, or other eliminable register. E.g. some
;; register holding an offset from the stack pointer. This is a
;; kludge, but there doesn't seem to be a way around it. Only
;; recognize them while reloading.
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=r,&r")
(plus:DI (plus:DI (match_operand:DI 1 "some_operand" "%r,r")
(match_operand:DI 2 "some_operand" "%r,r"))
(match_operand:DI 3 "some_operand" "IOKL,r")))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" ""))
(match_operand:DI 3 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:SI 0 "some_operand" "=r,&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
(match_operand:SI 2 "const48_operand" "I,I"))
(match_operand:SI 3 "some_operand" "%r,r"))
(match_operand:SI 4 "some_operand" "IOKL,r")))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
(match_operand:SI 3 "register_operand" ""))
(match_operand:SI 4 "add_operand" "rIOKL")))]
"reload_completed"
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
"")
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=r,&r")
(sign_extend:DI
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
(match_operand:SI 2 "const48_operand" "I,I"))
(match_operand:SI 3 "some_operand" "%r,r"))
(match_operand:SI 4 "some_operand" "IO,r"))))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
(match_operand:SI 3 "register_operand" ""))
(match_operand:SI 4 "sext_add_operand" ""))))]
"reload_completed"
[(set (match_dup 5)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
"operands[5] = gen_lowpart (SImode, operands[0]);")
(define_insn ""
[(set (match_operand:DI 0 "some_operand" "=r,&r")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ,rJ")
(match_operand:DI 2 "const48_operand" "I,I"))
(match_operand:DI 3 "some_operand" "%r,r"))
(match_operand:DI 4 "some_operand" "IOKL,r")))]
"reload_in_progress"
"#")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "const48_operand" ""))
(match_operand:DI 3 "register_operand" ""))
(match_operand:DI 4 "add_operand" "")))]
"reload_completed"
[(set (match_dup 0)
(plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
"")
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]