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alpha.c (aligned_memory_operand): Check MEM_ALIGN, don't check memory mode. 

* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
        don't check memory mode.
        (unaligned_memory_operand): Likewise.
        (reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
        abort for op0 not MEM.

        * config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
        is not a reg, copy to a scratch first.
        (aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
        unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
        unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
        (reload_inqi, reload_inhi): Fix mode of op0.
        (reload_inqi_help, reload_inhi_help, reload_outqi_help,
        reload_outhi_help): Likewise.  Use define_insn_and_split.

        * config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
        as well as $29 dead.

From-SVN: r76172
This commit is contained in:
Richard Henderson 2004-01-19 11:49:33 -08:00 committed by Richard Henderson
parent c9a5b62460
commit 62e882937c
3 changed files with 101 additions and 86 deletions
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20
gcc/ChangeLog
View File

@ -1,3 +1,23 @@
2004-01-19 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.c (aligned_memory_operand): Check MEM_ALIGN,
don't check memory mode.
(unaligned_memory_operand): Likewise.
(reload_inqi, reload_inhi, reload_outqi, reload_outhi): Don't
abort for op0 not MEM.
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
* config/alpha/alpha.md (call peepholes): Check for REG_NORETURN
as well as $29 dead.
2004-01-19 Eric Botcazou <ebotcazou@libertysurf.fr>
* config/sparc/sol2.h (ASM_DECLARE_OBJECT_NAME): New. Emit

49
gcc/config/alpha/alpha.c
View File

@ -1219,9 +1219,10 @@ aligned_memory_operand (rtx op, enum machine_mode mode)
}
}
if (GET_CODE (op) != MEM
|| GET_MODE (op) != mode)
if (GET_CODE (op) != MEM)
return 0;
if (MEM_ALIGN (op) >= 32)
return 1;
op = XEXP (op, 0);
/* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
@ -1261,8 +1262,9 @@ unaligned_memory_operand (rtx op, enum machine_mode mode)
}
}
if (GET_CODE (op) != MEM
|| GET_MODE (op) != mode)
if (GET_CODE (op) != MEM)
return 0;
if (MEM_ALIGN (op) >= 32)
return 0;
op = XEXP (op, 0);
@ -2876,13 +2878,24 @@ alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
{
rtx aligned_mem, bitnum;
rtx scratch = gen_reg_rtx (SImode);
rtx subtarget;
bool copyout;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
subtarget = operands[0];
if (GET_CODE (subtarget) == REG)
subtarget = gen_lowpart (DImode, subtarget), copyout = false;
else
subtarget = gen_reg_rtx (DImode), copyout = true;
emit_insn ((mode == QImode
? gen_aligned_loadqi
: gen_aligned_loadhi)
(operands[0], aligned_mem, bitnum, scratch));
(subtarget, aligned_mem, bitnum, scratch));
if (copyout)
emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
}
}
else
@ -2891,16 +2904,28 @@ alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
code depend on parameter evaluation order which will cause
bootstrap failures. */
rtx temp1 = gen_reg_rtx (DImode);
rtx temp2 = gen_reg_rtx (DImode);
rtx seq = ((mode == QImode
? gen_unaligned_loadqi
: gen_unaligned_loadhi)
(operands[0], get_unaligned_address (operands[1], 0),
temp1, temp2));
rtx temp1, temp2, seq, subtarget;
bool copyout;
temp1 = gen_reg_rtx (DImode);
temp2 = gen_reg_rtx (DImode);
subtarget = operands[0];
if (GET_CODE (subtarget) == REG)
subtarget = gen_lowpart (DImode, subtarget), copyout = false;
else
subtarget = gen_reg_rtx (DImode), copyout = true;
seq = ((mode == QImode
? gen_unaligned_loadqi
: gen_unaligned_loadhi)
(subtarget, get_unaligned_address (operands[1], 0),
temp1, temp2));
alpha_set_memflags (seq, operands[1]);
emit_insn (seq);
if (copyout)
emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
}
return true;
}

118
gcc/config/alpha/alpha.md
View File

@ -4718,7 +4718,8 @@
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
&& ! samegp_function_operand (operands[0], Pmode)
&& peep2_regno_dead_p (1, 29)"
&& (peep2_regno_dead_p (1, 29)
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
[(parallel [(call (mem:DI (match_dup 2))
(match_dup 1))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
@ -4748,7 +4749,8 @@
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
&& ! samegp_function_operand (operands[0], Pmode)
&& ! peep2_regno_dead_p (1, 29)"
&& ! (peep2_regno_dead_p (1, 29)
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
[(parallel [(call (mem:DI (match_dup 2))
(match_dup 1))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
@ -5708,7 +5710,7 @@
(define_expand "aligned_loadqi"
[(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 1 "memory_operand" ""))
(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 8)
(match_operand:DI 2 "const_int_operand" "")))]
@ -5719,7 +5721,7 @@
(define_expand "aligned_loadhi"
[(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 1 "memory_operand" ""))
(set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 16)
(match_operand:DI 2 "const_int_operand" "")))]
@ -5735,7 +5737,7 @@
;; operand 3 can overlap the input and output registers.
(define_expand "unaligned_loadqi"
[(use (match_operand:QI 0 "register_operand" ""))
[(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))
(use (match_operand:DI 2 "register_operand" ""))
(use (match_operand:DI 3 "register_operand" ""))]
@ -5756,7 +5758,7 @@
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 8)
(ashift:DI (match_dup 3) (const_int 3))))]
@ -5769,7 +5771,7 @@
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 8)
(minus:DI
@ -5779,7 +5781,7 @@
"")
(define_expand "unaligned_loadhi"
[(use (match_operand:QI 0 "register_operand" ""))
[(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))
(use (match_operand:DI 2 "register_operand" ""))
(use (match_operand:DI 3 "register_operand" ""))]
@ -5800,7 +5802,7 @@
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 16)
(ashift:DI (match_dup 3) (const_int 3))))]
@ -5813,7 +5815,7 @@
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(plus:DI (match_dup 1) (const_int 1)))
(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 16)
(minus:DI
@ -6008,9 +6010,6 @@
{
rtx scratch, seq;
if (GET_CODE (operands[1]) != MEM)
abort ();
if (aligned_memory_operand (operands[1], QImode))
{
seq = gen_reload_inqi_help (operands[0], operands[1],
@ -6029,8 +6028,8 @@
scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
addr = get_unaligned_address (operands[1], 0);
seq = gen_unaligned_loadqi (operands[0], addr, scratch,
gen_rtx_REG (DImode, REGNO (operands[0])));
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
alpha_set_memflags (seq, operands[1]);
}
emit_insn (seq);
@ -6045,9 +6044,6 @@
{
rtx scratch, seq;
if (GET_CODE (operands[1]) != MEM)
abort ();
if (aligned_memory_operand (operands[1], HImode))
{
seq = gen_reload_inhi_help (operands[0], operands[1],
@ -6066,8 +6062,8 @@
scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
addr = get_unaligned_address (operands[1], 0);
seq = gen_unaligned_loadhi (operands[0], addr, scratch,
gen_rtx_REG (DImode, REGNO (operands[0])));
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
alpha_set_memflags (seq, operands[1]);
}
emit_insn (seq);
@ -6080,9 +6076,6 @@
(match_operand:TI 2 "register_operand" "=&r")])]
"! TARGET_BWX"
{
if (GET_CODE (operands[0]) != MEM)
abort ();
if (aligned_memory_operand (operands[0], QImode))
{
emit_insn (gen_reload_outqi_help
@ -6115,9 +6108,6 @@
(match_operand:TI 2 "register_operand" "=&r")])]
"! TARGET_BWX"
{
if (GET_CODE (operands[0]) != MEM)
abort ();
if (aligned_memory_operand (operands[0], HImode))
{
emit_insn (gen_reload_outhi_help
@ -6148,71 +6138,47 @@
;; always get a proper address for a stack slot during reload_foo
;; expansion, so we must delay our address manipulations until after.
(define_insn "reload_inqi_help"
(define_insn_and_split "reload_inqi_help"
[(set (match_operand:QI 0 "register_operand" "=r")
(match_operand:QI 1 "memory_operand" "m"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#")
(define_insn "reload_inhi_help"
[(set (match_operand:HI 0 "register_operand" "=r")
(match_operand:HI 1 "memory_operand" "m"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#")
(define_insn "reload_outqi_help"
[(set (match_operand:QI 0 "memory_operand" "=m")
(match_operand:QI 1 "register_operand" "r"))
(clobber (match_operand:SI 2 "register_operand" "=r"))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#")
(define_insn "reload_outhi_help"
[(set (match_operand:HI 0 "memory_operand" "=m")
(match_operand:HI 1 "register_operand" "r"))
(clobber (match_operand:SI 2 "register_operand" "=r"))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#")
(define_split
[(set (match_operand:QI 0 "register_operand" "")
(match_operand:QI 1 "memory_operand" ""))
(clobber (match_operand:SI 2 "register_operand" ""))]
"#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
operands[0] = gen_lowpart (DImode, operands[0]);
emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
operands[2]));
DONE;
})
(define_split
[(set (match_operand:HI 0 "register_operand" "")
(match_operand:HI 1 "memory_operand" ""))
(clobber (match_operand:SI 2 "register_operand" ""))]
(define_insn_and_split "reload_inhi_help"
[(set (match_operand:HI 0 "register_operand" "=r")
(match_operand:HI 1 "memory_operand" "m"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
operands[0] = gen_lowpart (DImode, operands[0]);
emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
operands[2]));
DONE;
})
(define_split
[(set (match_operand:QI 0 "memory_operand" "")
(match_operand:QI 1 "register_operand" ""))
(clobber (match_operand:SI 2 "register_operand" ""))
(clobber (match_operand:SI 3 "register_operand" ""))]
(define_insn_and_split "reload_outqi_help"
[(set (match_operand:QI 0 "memory_operand" "=m")
(match_operand:QI 1 "register_operand" "r"))
(clobber (match_operand:SI 2 "register_operand" "=r"))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
@ -6223,11 +6189,13 @@
DONE;
})
(define_split
[(set (match_operand:HI 0 "memory_operand" "")
(match_operand:HI 1 "register_operand" ""))
(clobber (match_operand:SI 2 "register_operand" ""))
(clobber (match_operand:SI 3 "register_operand" ""))]
(define_insn_and_split "reload_outhi_help"
[(set (match_operand:HI 0 "memory_operand" "=m")
(match_operand:HI 1 "register_operand" "r"))
(clobber (match_operand:SI 2 "register_operand" "=r"))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
"#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
@ -7895,7 +7863,8 @@
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
&& ! samegp_function_operand (operands[1], Pmode)
&& peep2_regno_dead_p (1, 29)"
&& (peep2_regno_dead_p (1, 29)
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(match_dup 2)))
@ -7927,7 +7896,8 @@
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
&& ! samegp_function_operand (operands[1], Pmode)
&& ! peep2_regno_dead_p (1, 29)"
&& ! (peep2_regno_dead_p (1, 29)
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(match_dup 2)))