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arm.c (arm_print_operand): Use MEM_SIZE to get the size of a '%A' memory reference. 

gcc/
	* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
	size of a '%A' memory reference.
	(T_DREG, T_QREG): New neon_builtin_type_bits.
	(arm_init_neon_builtins): Assert that the load and store operands
	are neon_struct_operands.
	(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
	(NEON_ARG_MEMORY): New builtin_arg.
	(neon_dereference_pointer): New function.
	(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
	Handle NEON_ARG_MEMORY.
	(arm_expand_neon_builtin): Update after above interface changes.
	Use NEON_ARG_MEMORY for loads and stores.
	* config/arm/predicates.md (neon_struct_operand): New predicate.
	* config/arm/iterators.md (V_two_elem): Tweak formatting.
	(V_three_elem): Use BLKmode for accesses that have no associated mode.
	(V_four_elem): Tweak formatting.
	* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
	(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
	(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
	(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
	(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
	(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
	(neon_vst4<mode>): Replace pointer operand with a memory operand.
	Use %A in the output template.
	(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
	(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
	(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
	the width of the memory access.  Remove post-increment.
	* config/arm/neon-testgen.ml: Allow addresses to have an alignment.

gcc/testsuite/
	* gcc.target/arm/neon-vld3-1.c: New test.
	* gcc.target/arm/neon-vst3-1.c: New test.
	* gcc.target/arm/neon/v*.c: Regenerate.

From-SVN: r172314
This commit is contained in:
Richard Sandiford 2011-04-12 12:19:38 +00:00 committed by Richard Sandiford
parent e5db8f2fde
commit 6308e208c2
362 changed files with 782 additions and 612 deletions
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32
gcc/ChangeLog
View File

@ -1,3 +1,35 @@
2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
size of a '%A' memory reference.
(T_DREG, T_QREG): New neon_builtin_type_bits.
(arm_init_neon_builtins): Assert that the load and store operands
are neon_struct_operands.
(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
(NEON_ARG_MEMORY): New builtin_arg.
(neon_dereference_pointer): New function.
(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
Handle NEON_ARG_MEMORY.
(arm_expand_neon_builtin): Update after above interface changes.
Use NEON_ARG_MEMORY for loads and stores.
* config/arm/predicates.md (neon_struct_operand): New predicate.
* config/arm/iterators.md (V_two_elem): Tweak formatting.
(V_three_elem): Use BLKmode for accesses that have no associated mode.
(V_four_elem): Tweak formatting.
* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
(neon_vst4<mode>): Replace pointer operand with a memory operand.
Use %A in the output template.
(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
the width of the memory access. Remove post-increment.
* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
2011-04-12 Nick Clifton <nickc@redhat.com> 2011-04-12 Nick Clifton <nickc@redhat.com>
* config/v850/v850.c (expand_prologue): Do not use the CALLT * config/v850/v850.c (expand_prologue): Do not use the CALLT

166
gcc/config/arm/arm.c
View File

@ -16566,7 +16566,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
{ {
rtx addr; rtx addr;
bool postinc = FALSE; bool postinc = FALSE;
unsigned align, modesize, align_bits; unsigned align, memsize, align_bits;
gcc_assert (GET_CODE (x) == MEM); gcc_assert (GET_CODE (x) == MEM);
addr = XEXP (x, 0); addr = XEXP (x, 0);
@ -16581,12 +16581,12 @@ arm_print_operand (FILE *stream, rtx x, int code)
instruction (for some alignments) as an aid to the memory subsystem instruction (for some alignments) as an aid to the memory subsystem
of the target. */ of the target. */
align = MEM_ALIGN (x) >> 3; align = MEM_ALIGN (x) >> 3;
modesize = GET_MODE_SIZE (GET_MODE (x)); memsize = INTVAL (MEM_SIZE (x));
/* Only certain alignment specifiers are supported by the hardware. */ /* Only certain alignment specifiers are supported by the hardware. */
if (modesize == 16 && (align % 32) == 0) if (memsize == 16 && (align % 32) == 0)
align_bits = 256; align_bits = 256;
else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
align_bits = 128; align_bits = 128;
else if ((align % 8) == 0) else if ((align % 8) == 0)
align_bits = 64; align_bits = 64;
@ -18246,12 +18246,14 @@ enum neon_builtin_type_bits {
T_V2SI = 0x0004, T_V2SI = 0x0004,
T_V2SF = 0x0008, T_V2SF = 0x0008,
T_DI = 0x0010, T_DI = 0x0010,
T_DREG = 0x001F,
T_V16QI = 0x0020, T_V16QI = 0x0020,
T_V8HI = 0x0040, T_V8HI = 0x0040,
T_V4SI = 0x0080, T_V4SI = 0x0080,
T_V4SF = 0x0100, T_V4SF = 0x0100,
T_V2DI = 0x0200, T_V2DI = 0x0200,
T_TI = 0x0400, T_TI = 0x0400,
T_QREG = 0x07E0,
T_EI = 0x0800, T_EI = 0x0800,
T_OI = 0x1000 T_OI = 0x1000
}; };
@ -18897,10 +18899,9 @@ arm_init_neon_builtins (void)
if (is_load && k == 1) if (is_load && k == 1)
{ {
/* Neon load patterns always have the memory operand /* Neon load patterns always have the memory operand
(a SImode pointer) in the operand 1 position. We in the operand 1 position. */
want a const pointer to the element type in that gcc_assert (insn_data[icode].operand[k].predicate
position. */ == neon_struct_operand);
gcc_assert (insn_data[icode].operand[k].mode == SImode);
switch (1 << j) switch (1 << j)
{ {
@ -18935,10 +18936,9 @@ arm_init_neon_builtins (void)
else if (is_store && k == 0) else if (is_store && k == 0)
{ {
/* Similarly, Neon store patterns use operand 0 as /* Similarly, Neon store patterns use operand 0 as
the memory location to store to (a SImode pointer). the memory location to store to. */
Use a pointer to the element type of the store in gcc_assert (insn_data[icode].operand[k].predicate
that position. */ == neon_struct_operand);
gcc_assert (insn_data[icode].operand[k].mode == SImode);
switch (1 << j) switch (1 << j)
{ {
@ -19258,12 +19258,13 @@ neon_builtin_compare (const void *a, const void *b)
} }
static enum insn_code static enum insn_code
locate_neon_builtin_icode (int fcode, neon_itype *itype) locate_neon_builtin_icode (int fcode, neon_itype *itype,
enum neon_builtin_type_bits *type_bit)
{ {
neon_builtin_datum key neon_builtin_datum key
= { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 }; = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
neon_builtin_datum *found; neon_builtin_datum *found;
int idx; int idx, type, ntypes;
key.base_fcode = fcode; key.base_fcode = fcode;
found = (neon_builtin_datum *) found = (neon_builtin_datum *)
@ -19276,20 +19277,84 @@ locate_neon_builtin_icode (int fcode, neon_itype *itype)
if (itype) if (itype)
*itype = found->itype; *itype = found->itype;
if (type_bit)
{
ntypes = 0;
for (type = 0; type < T_MAX; type++)
if (found->bits & (1 << type))
{
if (ntypes == idx)
break;
ntypes++;
}
gcc_assert (type < T_MAX);
*type_bit = (enum neon_builtin_type_bits) (1 << type);
}
return found->codes[idx]; return found->codes[idx];
} }
typedef enum { typedef enum {
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
NEON_ARG_MEMORY,
NEON_ARG_STOP NEON_ARG_STOP
} builtin_arg; } builtin_arg;
#define NEON_MAX_BUILTIN_ARGS 5 #define NEON_MAX_BUILTIN_ARGS 5
/* EXP is a pointer argument to a Neon load or store intrinsic. Derive
and return an expression for the accessed memory.
The intrinsic function operates on a block of registers that has
mode REG_MODE. This block contains vectors of type TYPE_BIT.
The function references the memory at EXP in mode MEM_MODE;
this mode may be BLKmode if no more suitable mode is available. */
static tree
neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
enum machine_mode reg_mode,
enum neon_builtin_type_bits type_bit)
{
HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
tree elem_type, upper_bound, array_type;
/* Work out the size of the register block in bytes. */
reg_size = GET_MODE_SIZE (reg_mode);
/* Work out the size of each vector in bytes. */
gcc_assert (type_bit & (T_DREG | T_QREG));
vector_size = (type_bit & T_QREG ? 16 : 8);
/* Work out how many vectors there are. */
gcc_assert (reg_size % vector_size == 0);
nvectors = reg_size / vector_size;
/* Work out how many elements are being loaded or stored.
MEM_MODE == REG_MODE implies a one-to-one mapping between register
and memory elements; anything else implies a lane load or store. */
if (mem_mode == reg_mode)
nelems = vector_size * nvectors;
else
nelems = nvectors;
/* Work out the type of each element. */
gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
elem_type = TREE_TYPE (TREE_TYPE (exp));
/* Create a type that describes the full access. */
upper_bound = build_int_cst (size_type_node, nelems - 1);
array_type = build_array_type (elem_type, build_index_type (upper_bound));
/* Dereference EXP using that type. */
exp = convert (build_pointer_type (array_type), exp);
return fold_build2 (MEM_REF, array_type, exp,
build_int_cst (TREE_TYPE (exp), 0));
}
/* Expand a Neon builtin. */ /* Expand a Neon builtin. */
static rtx static rtx
arm_expand_neon_args (rtx target, int icode, int have_retval, arm_expand_neon_args (rtx target, int icode, int have_retval,
enum neon_builtin_type_bits type_bit,
tree exp, ...) tree exp, ...)
{ {
va_list ap; va_list ap;
@ -19298,7 +19363,9 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
rtx op[NEON_MAX_BUILTIN_ARGS]; rtx op[NEON_MAX_BUILTIN_ARGS];
enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode tmode = insn_data[icode].operand[0].mode;
enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
enum machine_mode other_mode;
int argc = 0; int argc = 0;
int opno;
if (have_retval if (have_retval
&& (!target && (!target
@ -19316,26 +19383,46 @@ arm_expand_neon_args (rtx target, int icode, int have_retval,
break; break;
else else
{ {
opno = argc + have_retval;
mode[argc] = insn_data[icode].operand[opno].mode;
arg[argc] = CALL_EXPR_ARG (exp, argc); arg[argc] = CALL_EXPR_ARG (exp, argc);
if (thisarg == NEON_ARG_MEMORY)
{
other_mode = insn_data[icode].operand[1 - opno].mode;
arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
other_mode, type_bit);
}
op[argc] = expand_normal (arg[argc]); op[argc] = expand_normal (arg[argc]);
mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
switch (thisarg) switch (thisarg)
{ {
case NEON_ARG_COPY_TO_REG: case NEON_ARG_COPY_TO_REG:
/*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
if (!(*insn_data[icode].operand[argc + have_retval].predicate) if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc])) (op[argc], mode[argc]))
op[argc] = copy_to_mode_reg (mode[argc], op[argc]); op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
break; break;
case NEON_ARG_CONSTANT: case NEON_ARG_CONSTANT:
/* FIXME: This error message is somewhat unhelpful. */ /* FIXME: This error message is somewhat unhelpful. */
if (!(*insn_data[icode].operand[argc + have_retval].predicate) if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc])) (op[argc], mode[argc]))
error ("argument must be a constant"); error ("argument must be a constant");
break; break;
case NEON_ARG_MEMORY:
gcc_assert (MEM_P (op[argc]));
PUT_MODE (op[argc], mode[argc]);
/* ??? arm_neon.h uses the same built-in functions for signed
and unsigned accesses, casting where necessary. This isn't
alias safe. */
set_mem_alias_set (op[argc], 0);
if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc]))
op[argc] = (replace_equiv_address
(op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
break;
case NEON_ARG_STOP: case NEON_ARG_STOP:
gcc_unreachable (); gcc_unreachable ();
} }
@ -19414,14 +19501,15 @@ static rtx
arm_expand_neon_builtin (int fcode, tree exp, rtx target) arm_expand_neon_builtin (int fcode, tree exp, rtx target)
{ {
neon_itype itype; neon_itype itype;
enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); enum neon_builtin_type_bits type_bit;
enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
switch (itype) switch (itype)
{ {
case NEON_UNOP: case NEON_UNOP:
case NEON_CONVERT: case NEON_CONVERT:
case NEON_DUPLANE: case NEON_DUPLANE:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_BINOP: case NEON_BINOP:
@ -19431,90 +19519,90 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
case NEON_SCALARMULH: case NEON_SCALARMULH:
case NEON_SHIFTINSERT: case NEON_SHIFTINSERT:
case NEON_LOGICBINOP: case NEON_LOGICBINOP:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP); NEON_ARG_STOP);
case NEON_TERNOP: case NEON_TERNOP:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT, NEON_ARG_STOP); NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_GETLANE: case NEON_GETLANE:
case NEON_FIXCONV: case NEON_FIXCONV:
case NEON_SHIFTIMM: case NEON_SHIFTIMM:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
NEON_ARG_STOP); NEON_ARG_STOP);
case NEON_CREATE: case NEON_CREATE:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_DUP: case NEON_DUP:
case NEON_SPLIT: case NEON_SPLIT:
case NEON_REINTERP: case NEON_REINTERP:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_COMBINE: case NEON_COMBINE:
case NEON_VTBL: case NEON_VTBL:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_RESULTPAIR: case NEON_RESULTPAIR:
return arm_expand_neon_args (target, icode, 0, exp, return arm_expand_neon_args (target, icode, 0, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_STOP); NEON_ARG_STOP);
case NEON_LANEMUL: case NEON_LANEMUL:
case NEON_LANEMULL: case NEON_LANEMULL:
case NEON_LANEMULH: case NEON_LANEMULH:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_CONSTANT, NEON_ARG_STOP); NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_LANEMAC: case NEON_LANEMAC:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_SHIFTACC: case NEON_SHIFTACC:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_CONSTANT, NEON_ARG_STOP); NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_SCALARMAC: case NEON_SCALARMAC:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT, NEON_ARG_STOP); NEON_ARG_CONSTANT, NEON_ARG_STOP);
case NEON_SELECT: case NEON_SELECT:
case NEON_VTBX: case NEON_VTBX:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
NEON_ARG_STOP); NEON_ARG_STOP);
case NEON_LOAD1: case NEON_LOAD1:
case NEON_LOADSTRUCT: case NEON_LOADSTRUCT:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); NEON_ARG_MEMORY, NEON_ARG_STOP);
case NEON_LOAD1LANE: case NEON_LOAD1LANE:
case NEON_LOADSTRUCTLANE: case NEON_LOADSTRUCTLANE:
return arm_expand_neon_args (target, icode, 1, exp, return arm_expand_neon_args (target, icode, 1, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP); NEON_ARG_STOP);
case NEON_STORE1: case NEON_STORE1:
case NEON_STORESTRUCT: case NEON_STORESTRUCT:
return arm_expand_neon_args (target, icode, 0, exp, return arm_expand_neon_args (target, icode, 0, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
case NEON_STORE1LANE: case NEON_STORE1LANE:
case NEON_STORESTRUCTLANE: case NEON_STORESTRUCTLANE:
return arm_expand_neon_args (target, icode, 0, exp, return arm_expand_neon_args (target, icode, 0, type_bit, exp,
NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
NEON_ARG_STOP); NEON_ARG_STOP);
} }

10
gcc/config/arm/iterators.md
View File

@ -201,12 +201,10 @@
(DI "V2DI") (V2DI "V2DI")]) (DI "V2DI") (V2DI "V2DI")])
;; Similar, for three elements. ;; Similar, for three elements.
;; ??? Should we define extra modes so that sizes of all three-element (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
;; accesses can be accurately represented? (V4HI "BLK") (V8HI "BLK")
(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") (V2SI "BLK") (V4SI "BLK")
(V4HI "V4HI") (V8HI "V4HI") (V2SF "BLK") (V4SF "BLK")
(V2SI "V4SI") (V4SI "V4SI")
(V2SF "V4SF") (V4SF "V4SF")
(DI "EI") (V2DI "EI")]) (DI "EI") (V2DI "EI")])
;; Similar, for four elements. ;; Similar, for four elements.

2
gcc/config/arm/neon-testgen.ml
View File

@ -177,7 +177,7 @@ let rec analyze_shape shape =
let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
"\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}" "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
| (PtrTo elt | CstPtrTo elt) -> | (PtrTo elt | CstPtrTo elt) ->
"\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]" "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
| Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
| Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
| All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]" | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"

300
gcc/config/arm/neon.md
View File

@ -4260,16 +4260,16 @@
(define_insn "neon_vld1<mode>" (define_insn "neon_vld1<mode>"
[(set (match_operand:VDQX 0 "s_register_operand" "=w") [(set (match_operand:VDQX 0 "s_register_operand" "=w")
(unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))] (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
UNSPEC_VLD1))] UNSPEC_VLD1))]
"TARGET_NEON" "TARGET_NEON"
"vld1.<V_sz_elem>\t%h0, [%1]" "vld1.<V_sz_elem>\t%h0, %A1"
[(set_attr "neon_type" "neon_vld1_1_2_regs")] [(set_attr "neon_type" "neon_vld1_1_2_regs")]
) )
(define_insn "neon_vld1_lane<mode>" (define_insn "neon_vld1_lane<mode>"
[(set (match_operand:VDX 0 "s_register_operand" "=w") [(set (match_operand:VDX 0 "s_register_operand" "=w")
(unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
(match_operand:VDX 2 "s_register_operand" "0") (match_operand:VDX 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")] (match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VLD1_LANE))] UNSPEC_VLD1_LANE))]
@ -4280,9 +4280,9 @@
if (lane < 0 || lane >= max) if (lane < 0 || lane >= max)
error ("lane out of range"); error ("lane out of range");
if (max == 1) if (max == 1)
return "vld1.<V_sz_elem>\t%P0, [%1]"; return "vld1.<V_sz_elem>\t%P0, %A1";
else else
return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]"; return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2)) (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
@ -4292,7 +4292,7 @@
(define_insn "neon_vld1_lane<mode>" (define_insn "neon_vld1_lane<mode>"
[(set (match_operand:VQX 0 "s_register_operand" "=w") [(set (match_operand:VQX 0 "s_register_operand" "=w")
(unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
(match_operand:VQX 2 "s_register_operand" "0") (match_operand:VQX 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")] (match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VLD1_LANE))] UNSPEC_VLD1_LANE))]
@ -4311,9 +4311,9 @@
} }
operands[0] = gen_rtx_REG (<V_HALF>mode, regno); operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
if (max == 2) if (max == 2)
return "vld1.<V_sz_elem>\t%P0, [%1]"; return "vld1.<V_sz_elem>\t%P0, %A1";
else else
return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]"; return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2)) (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
@ -4323,14 +4323,14 @@
(define_insn "neon_vld1_dup<mode>" (define_insn "neon_vld1_dup<mode>"
[(set (match_operand:VDX 0 "s_register_operand" "=w") [(set (match_operand:VDX 0 "s_register_operand" "=w")
(unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))] (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
UNSPEC_VLD1_DUP))] UNSPEC_VLD1_DUP))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (GET_MODE_NUNITS (<MODE>mode) > 1) if (GET_MODE_NUNITS (<MODE>mode) > 1)
return "vld1.<V_sz_elem>\t{%P0[]}, [%1]"; return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
else else
return "vld1.<V_sz_elem>\t%h0, [%1]"; return "vld1.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
@ -4340,14 +4340,14 @@
(define_insn "neon_vld1_dup<mode>" (define_insn "neon_vld1_dup<mode>"
[(set (match_operand:VQX 0 "s_register_operand" "=w") [(set (match_operand:VQX 0 "s_register_operand" "=w")
(unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))] (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
UNSPEC_VLD1_DUP))] UNSPEC_VLD1_DUP))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (GET_MODE_NUNITS (<MODE>mode) > 2) if (GET_MODE_NUNITS (<MODE>mode) > 2)
return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]"; return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
else else
return "vld1.<V_sz_elem>\t%h0, [%1]"; return "vld1.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
@ -4356,15 +4356,15 @@
) )
(define_insn "neon_vst1<mode>" (define_insn "neon_vst1<mode>"
[(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")] (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
UNSPEC_VST1))] UNSPEC_VST1))]
"TARGET_NEON" "TARGET_NEON"
"vst1.<V_sz_elem>\t%h1, [%0]" "vst1.<V_sz_elem>\t%h1, %A0"
[(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
(define_insn "neon_vst1_lane<mode>" (define_insn "neon_vst1_lane<mode>"
[(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
(vec_select:<V_elem> (vec_select:<V_elem>
(match_operand:VDX 1 "s_register_operand" "w") (match_operand:VDX 1 "s_register_operand" "w")
(parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
@ -4375,9 +4375,9 @@
if (lane < 0 || lane >= max) if (lane < 0 || lane >= max)
error ("lane out of range"); error ("lane out of range");
if (max == 1) if (max == 1)
return "vst1.<V_sz_elem>\t{%P1}, [%0]"; return "vst1.<V_sz_elem>\t{%P1}, %A0";
else else
return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]"; return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1)) (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
@ -4385,7 +4385,7 @@
(const_string "neon_vst1_vst2_lane")))]) (const_string "neon_vst1_vst2_lane")))])
(define_insn "neon_vst1_lane<mode>" (define_insn "neon_vst1_lane<mode>"
[(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
(vec_select:<V_elem> (vec_select:<V_elem>
(match_operand:VQX 1 "s_register_operand" "w") (match_operand:VQX 1 "s_register_operand" "w")
(parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
@ -4404,24 +4404,24 @@
} }
operands[1] = gen_rtx_REG (<V_HALF>mode, regno); operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
if (max == 2) if (max == 2)
return "vst1.<V_sz_elem>\t{%P1}, [%0]"; return "vst1.<V_sz_elem>\t{%P1}, %A0";
else else
return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]"; return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
} }
[(set_attr "neon_type" "neon_vst1_vst2_lane")] [(set_attr "neon_type" "neon_vst1_vst2_lane")]
) )
(define_insn "neon_vld2<mode>" (define_insn "neon_vld2<mode>"
[(set (match_operand:TI 0 "s_register_operand" "=w") [(set (match_operand:TI 0 "s_register_operand" "=w")
(unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r")) (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD2))] UNSPEC_VLD2))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (<V_sz_elem> == 64) if (<V_sz_elem> == 64)
return "vld1.64\t%h0, [%1]"; return "vld1.64\t%h0, %A1";
else else
return "vld2.<V_sz_elem>\t%h0, [%1]"; return "vld2.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
@ -4431,16 +4431,16 @@
(define_insn "neon_vld2<mode>" (define_insn "neon_vld2<mode>"
[(set (match_operand:OI 0 "s_register_operand" "=w") [(set (match_operand:OI 0 "s_register_operand" "=w")
(unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD2))] UNSPEC_VLD2))]
"TARGET_NEON" "TARGET_NEON"
"vld2.<V_sz_elem>\t%h0, [%1]" "vld2.<V_sz_elem>\t%h0, %A1"
[(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]) [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
(define_insn "neon_vld2_lane<mode>" (define_insn "neon_vld2_lane<mode>"
[(set (match_operand:TI 0 "s_register_operand" "=w") [(set (match_operand:TI 0 "s_register_operand" "=w")
(unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
(match_operand:TI 2 "s_register_operand" "0") (match_operand:TI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@ -4457,7 +4457,7 @@
ops[1] = gen_rtx_REG (DImode, regno + 2); ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = operands[1]; ops[2] = operands[1];
ops[3] = operands[3]; ops[3] = operands[3];
output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops); output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vld1_vld2_lane")] [(set_attr "neon_type" "neon_vld1_vld2_lane")]
@ -4465,7 +4465,7 @@
(define_insn "neon_vld2_lane<mode>" (define_insn "neon_vld2_lane<mode>"
[(set (match_operand:OI 0 "s_register_operand" "=w") [(set (match_operand:OI 0 "s_register_operand" "=w")
(unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
(match_operand:OI 2 "s_register_operand" "0") (match_operand:OI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@ -4487,7 +4487,7 @@
ops[1] = gen_rtx_REG (DImode, regno + 4); ops[1] = gen_rtx_REG (DImode, regno + 4);
ops[2] = operands[1]; ops[2] = operands[1];
ops[3] = GEN_INT (lane); ops[3] = GEN_INT (lane);
output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops); output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vld1_vld2_lane")] [(set_attr "neon_type" "neon_vld1_vld2_lane")]
@ -4495,15 +4495,15 @@
(define_insn "neon_vld2_dup<mode>" (define_insn "neon_vld2_dup<mode>"
[(set (match_operand:TI 0 "s_register_operand" "=w") [(set (match_operand:TI 0 "s_register_operand" "=w")
(unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD2_DUP))] UNSPEC_VLD2_DUP))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (GET_MODE_NUNITS (<MODE>mode) > 1) if (GET_MODE_NUNITS (<MODE>mode) > 1)
return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]"; return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
else else
return "vld1.<V_sz_elem>\t%h0, [%1]"; return "vld1.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
@ -4512,16 +4512,16 @@
) )
(define_insn "neon_vst2<mode>" (define_insn "neon_vst2<mode>"
[(set (mem:TI (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
(unspec:TI [(match_operand:TI 1 "s_register_operand" "w") (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST2))] UNSPEC_VST2))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (<V_sz_elem> == 64) if (<V_sz_elem> == 64)
return "vst1.64\t%h1, [%0]"; return "vst1.64\t%h1, %A0";
else else
return "vst2.<V_sz_elem>\t%h1, [%0]"; return "vst2.<V_sz_elem>\t%h1, %A0";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
@ -4530,17 +4530,17 @@
) )
(define_insn "neon_vst2<mode>" (define_insn "neon_vst2<mode>"
[(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
(unspec:OI [(match_operand:OI 1 "s_register_operand" "w") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST2))] UNSPEC_VST2))]
"TARGET_NEON" "TARGET_NEON"
"vst2.<V_sz_elem>\t%h1, [%0]" "vst2.<V_sz_elem>\t%h1, %A0"
[(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")] [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
) )
(define_insn "neon_vst2_lane<mode>" (define_insn "neon_vst2_lane<mode>"
[(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
(unspec:<V_two_elem> (unspec:<V_two_elem>
[(match_operand:TI 1 "s_register_operand" "w") [(match_operand:TI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")
@ -4558,14 +4558,14 @@
ops[1] = gen_rtx_REG (DImode, regno); ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 2); ops[2] = gen_rtx_REG (DImode, regno + 2);
ops[3] = operands[2]; ops[3] = operands[2];
output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops); output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vst1_vst2_lane")] [(set_attr "neon_type" "neon_vst1_vst2_lane")]
) )
(define_insn "neon_vst2_lane<mode>" (define_insn "neon_vst2_lane<mode>"
[(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
(unspec:<V_two_elem> (unspec:<V_two_elem>
[(match_operand:OI 1 "s_register_operand" "w") [(match_operand:OI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")
@ -4588,7 +4588,7 @@
ops[1] = gen_rtx_REG (DImode, regno); ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = GEN_INT (lane); ops[3] = GEN_INT (lane);
output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops); output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vst1_vst2_lane")] [(set_attr "neon_type" "neon_vst1_vst2_lane")]
@ -4596,15 +4596,15 @@
(define_insn "neon_vld3<mode>" (define_insn "neon_vld3<mode>"
[(set (match_operand:EI 0 "s_register_operand" "=w") [(set (match_operand:EI 0 "s_register_operand" "=w")
(unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r")) (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD3))] UNSPEC_VLD3))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (<V_sz_elem> == 64) if (<V_sz_elem> == 64)
return "vld1.64\t%h0, [%1]"; return "vld1.64\t%h0, %A1";
else else
return "vld3.<V_sz_elem>\t%h0, [%1]"; return "vld3.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
@ -4613,25 +4613,25 @@
) )
(define_expand "neon_vld3<mode>" (define_expand "neon_vld3<mode>"
[(match_operand:CI 0 "s_register_operand" "=w") [(match_operand:CI 0 "s_register_operand")
(match_operand:SI 1 "s_register_operand" "+r") (match_operand:CI 1 "neon_struct_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_NEON" "TARGET_NEON"
{ {
emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[1], operands[1])); rtx mem;
emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
operands[1], operands[1])); mem = adjust_address (operands[1], EImode, 0);
emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
DONE; DONE;
}) })
(define_insn "neon_vld3qa<mode>" (define_insn "neon_vld3qa<mode>"
[(set (match_operand:CI 0 "s_register_operand" "=w") [(set (match_operand:CI 0 "s_register_operand" "=w")
(unspec:CI [(mem:CI (match_operand:SI 2 "s_register_operand" "1")) (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD3A)) UNSPEC_VLD3A))]
(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_dup 2)
(const_int 24)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[0]); int regno = REGNO (operands[0]);
@ -4640,7 +4640,7 @@
ops[1] = gen_rtx_REG (DImode, regno + 4); ops[1] = gen_rtx_REG (DImode, regno + 4);
ops[2] = gen_rtx_REG (DImode, regno + 8); ops[2] = gen_rtx_REG (DImode, regno + 8);
ops[3] = operands[1]; ops[3] = operands[1];
output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops); output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vld3_vld4")] [(set_attr "neon_type" "neon_vld3_vld4")]
@ -4648,13 +4648,10 @@
(define_insn "neon_vld3qb<mode>" (define_insn "neon_vld3qb<mode>"
[(set (match_operand:CI 0 "s_register_operand" "=w") [(set (match_operand:CI 0 "s_register_operand" "=w")
(unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
(match_operand:CI 1 "s_register_operand" "0") (match_operand:CI 2 "s_register_operand" "0")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD3B)) UNSPEC_VLD3B))]
(set (match_operand:SI 2 "s_register_operand" "=r")
(plus:SI (match_dup 3)
(const_int 24)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[0]); int regno = REGNO (operands[0]);
@ -4662,8 +4659,8 @@
ops[0] = gen_rtx_REG (DImode, regno + 2); ops[0] = gen_rtx_REG (DImode, regno + 2);
ops[1] = gen_rtx_REG (DImode, regno + 6); ops[1] = gen_rtx_REG (DImode, regno + 6);
ops[2] = gen_rtx_REG (DImode, regno + 10); ops[2] = gen_rtx_REG (DImode, regno + 10);
ops[3] = operands[2]; ops[3] = operands[1];
output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops); output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vld3_vld4")] [(set_attr "neon_type" "neon_vld3_vld4")]
@ -4671,7 +4668,7 @@
(define_insn "neon_vld3_lane<mode>" (define_insn "neon_vld3_lane<mode>"
[(set (match_operand:EI 0 "s_register_operand" "=w") [(set (match_operand:EI 0 "s_register_operand" "=w")
(unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
(match_operand:EI 2 "s_register_operand" "0") (match_operand:EI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@ -4689,7 +4686,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = operands[1]; ops[3] = operands[1];
ops[4] = operands[3]; ops[4] = operands[3];
output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
ops); ops);
return ""; return "";
} }
@ -4698,7 +4695,7 @@
(define_insn "neon_vld3_lane<mode>" (define_insn "neon_vld3_lane<mode>"
[(set (match_operand:CI 0 "s_register_operand" "=w") [(set (match_operand:CI 0 "s_register_operand" "=w")
(unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
(match_operand:CI 2 "s_register_operand" "0") (match_operand:CI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@ -4721,7 +4718,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 8); ops[2] = gen_rtx_REG (DImode, regno + 8);
ops[3] = operands[1]; ops[3] = operands[1];
ops[4] = GEN_INT (lane); ops[4] = GEN_INT (lane);
output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
ops); ops);
return ""; return "";
} }
@ -4730,7 +4727,7 @@
(define_insn "neon_vld3_dup<mode>" (define_insn "neon_vld3_dup<mode>"
[(set (match_operand:EI 0 "s_register_operand" "=w") [(set (match_operand:EI 0 "s_register_operand" "=w")
(unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD3_DUP))] UNSPEC_VLD3_DUP))]
"TARGET_NEON" "TARGET_NEON"
@ -4743,11 +4740,11 @@
ops[1] = gen_rtx_REG (DImode, regno + 2); ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = operands[1]; ops[3] = operands[1];
output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops); output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
return ""; return "";
} }
else else
return "vld1.<V_sz_elem>\t%h0, [%1]"; return "vld1.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
@ -4755,16 +4752,16 @@
(const_string "neon_vld1_1_2_regs")))]) (const_string "neon_vld1_1_2_regs")))])
(define_insn "neon_vst3<mode>" (define_insn "neon_vst3<mode>"
[(set (mem:EI (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
(unspec:EI [(match_operand:EI 1 "s_register_operand" "w") (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST3))] UNSPEC_VST3))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (<V_sz_elem> == 64) if (<V_sz_elem> == 64)
return "vst1.64\t%h1, [%0]"; return "vst1.64\t%h1, %A0";
else else
return "vst3.<V_sz_elem>\t%h1, [%0]"; return "vst3.<V_sz_elem>\t%h1, %A0";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
@ -4772,62 +4769,60 @@
(const_string "neon_vst2_4_regs_vst3_vst4")))]) (const_string "neon_vst2_4_regs_vst3_vst4")))])
(define_expand "neon_vst3<mode>" (define_expand "neon_vst3<mode>"
[(match_operand:SI 0 "s_register_operand" "+r") [(match_operand:CI 0 "neon_struct_operand")
(match_operand:CI 1 "s_register_operand" "w") (match_operand:CI 1 "s_register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_NEON" "TARGET_NEON"
{ {
emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1])); rtx mem;
emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
mem = adjust_address (operands[0], EImode, 0);
emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
DONE; DONE;
}) })
(define_insn "neon_vst3qa<mode>" (define_insn "neon_vst3qa<mode>"
[(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
(unspec:EI [(match_operand:CI 2 "s_register_operand" "w") (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST3A)) UNSPEC_VST3A))]
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1)
(const_int 24)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[2]); int regno = REGNO (operands[1]);
rtx ops[4]; rtx ops[4];
ops[0] = operands[0]; ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno); ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = gen_rtx_REG (DImode, regno + 8); ops[3] = gen_rtx_REG (DImode, regno + 8);
output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops); output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
) )
(define_insn "neon_vst3qb<mode>" (define_insn "neon_vst3qb<mode>"
[(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
(unspec:EI [(match_operand:CI 2 "s_register_operand" "w") (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST3B)) UNSPEC_VST3B))]
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1)
(const_int 24)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[2]); int regno = REGNO (operands[1]);
rtx ops[4]; rtx ops[4];
ops[0] = operands[0]; ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno + 2); ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = gen_rtx_REG (DImode, regno + 6); ops[2] = gen_rtx_REG (DImode, regno + 6);
ops[3] = gen_rtx_REG (DImode, regno + 10); ops[3] = gen_rtx_REG (DImode, regno + 10);
output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops); output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
) )
(define_insn "neon_vst3_lane<mode>" (define_insn "neon_vst3_lane<mode>"
[(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
(unspec:<V_three_elem> (unspec:<V_three_elem>
[(match_operand:EI 1 "s_register_operand" "w") [(match_operand:EI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")
@ -4846,7 +4841,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 2); ops[2] = gen_rtx_REG (DImode, regno + 2);
ops[3] = gen_rtx_REG (DImode, regno + 4); ops[3] = gen_rtx_REG (DImode, regno + 4);
ops[4] = operands[2]; ops[4] = operands[2];
output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
ops); ops);
return ""; return "";
} }
@ -4854,7 +4849,7 @@
) )
(define_insn "neon_vst3_lane<mode>" (define_insn "neon_vst3_lane<mode>"
[(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
(unspec:<V_three_elem> (unspec:<V_three_elem>
[(match_operand:CI 1 "s_register_operand" "w") [(match_operand:CI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")
@ -4878,7 +4873,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = gen_rtx_REG (DImode, regno + 8); ops[3] = gen_rtx_REG (DImode, regno + 8);
ops[4] = GEN_INT (lane); ops[4] = GEN_INT (lane);
output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
ops); ops);
return ""; return "";
} }
@ -4886,15 +4881,15 @@
(define_insn "neon_vld4<mode>" (define_insn "neon_vld4<mode>"
[(set (match_operand:OI 0 "s_register_operand" "=w") [(set (match_operand:OI 0 "s_register_operand" "=w")
(unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD4))] UNSPEC_VLD4))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (<V_sz_elem> == 64) if (<V_sz_elem> == 64)
return "vld1.64\t%h0, [%1]"; return "vld1.64\t%h0, %A1";
else else
return "vld4.<V_sz_elem>\t%h0, [%1]"; return "vld4.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
@ -4903,25 +4898,25 @@
) )
(define_expand "neon_vld4<mode>" (define_expand "neon_vld4<mode>"
[(match_operand:XI 0 "s_register_operand" "=w") [(match_operand:XI 0 "s_register_operand")
(match_operand:SI 1 "s_register_operand" "+r") (match_operand:XI 1 "neon_struct_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_NEON" "TARGET_NEON"
{ {
emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[1], operands[1])); rtx mem;
emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
operands[1], operands[1])); mem = adjust_address (operands[1], OImode, 0);
emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
DONE; DONE;
}) })
(define_insn "neon_vld4qa<mode>" (define_insn "neon_vld4qa<mode>"
[(set (match_operand:XI 0 "s_register_operand" "=w") [(set (match_operand:XI 0 "s_register_operand" "=w")
(unspec:XI [(mem:XI (match_operand:SI 2 "s_register_operand" "1")) (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD4A)) UNSPEC_VLD4A))]
(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_dup 2)
(const_int 32)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[0]); int regno = REGNO (operands[0]);
@ -4931,7 +4926,7 @@
ops[2] = gen_rtx_REG (DImode, regno + 8); ops[2] = gen_rtx_REG (DImode, regno + 8);
ops[3] = gen_rtx_REG (DImode, regno + 12); ops[3] = gen_rtx_REG (DImode, regno + 12);
ops[4] = operands[1]; ops[4] = operands[1];
output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops); output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vld3_vld4")] [(set_attr "neon_type" "neon_vld3_vld4")]
@ -4939,13 +4934,10 @@
(define_insn "neon_vld4qb<mode>" (define_insn "neon_vld4qb<mode>"
[(set (match_operand:XI 0 "s_register_operand" "=w") [(set (match_operand:XI 0 "s_register_operand" "=w")
(unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
(match_operand:XI 1 "s_register_operand" "0") (match_operand:XI 2 "s_register_operand" "0")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD4B)) UNSPEC_VLD4B))]
(set (match_operand:SI 2 "s_register_operand" "=r")
(plus:SI (match_dup 3)
(const_int 32)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[0]); int regno = REGNO (operands[0]);
@ -4954,8 +4946,8 @@
ops[1] = gen_rtx_REG (DImode, regno + 6); ops[1] = gen_rtx_REG (DImode, regno + 6);
ops[2] = gen_rtx_REG (DImode, regno + 10); ops[2] = gen_rtx_REG (DImode, regno + 10);
ops[3] = gen_rtx_REG (DImode, regno + 14); ops[3] = gen_rtx_REG (DImode, regno + 14);
ops[4] = operands[2]; ops[4] = operands[1];
output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops); output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vld3_vld4")] [(set_attr "neon_type" "neon_vld3_vld4")]
@ -4963,7 +4955,7 @@
(define_insn "neon_vld4_lane<mode>" (define_insn "neon_vld4_lane<mode>"
[(set (match_operand:OI 0 "s_register_operand" "=w") [(set (match_operand:OI 0 "s_register_operand" "=w")
(unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
(match_operand:OI 2 "s_register_operand" "0") (match_operand:OI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@ -4982,7 +4974,7 @@
ops[3] = gen_rtx_REG (DImode, regno + 6); ops[3] = gen_rtx_REG (DImode, regno + 6);
ops[4] = operands[1]; ops[4] = operands[1];
ops[5] = operands[3]; ops[5] = operands[3];
output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
ops); ops);
return ""; return "";
} }
@ -4991,7 +4983,7 @@
(define_insn "neon_vld4_lane<mode>" (define_insn "neon_vld4_lane<mode>"
[(set (match_operand:XI 0 "s_register_operand" "=w") [(set (match_operand:XI 0 "s_register_operand" "=w")
(unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
(match_operand:XI 2 "s_register_operand" "0") (match_operand:XI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")
(unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@ -5015,7 +5007,7 @@
ops[3] = gen_rtx_REG (DImode, regno + 12); ops[3] = gen_rtx_REG (DImode, regno + 12);
ops[4] = operands[1]; ops[4] = operands[1];
ops[5] = GEN_INT (lane); ops[5] = GEN_INT (lane);
output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
ops); ops);
return ""; return "";
} }
@ -5024,7 +5016,7 @@
(define_insn "neon_vld4_dup<mode>" (define_insn "neon_vld4_dup<mode>"
[(set (match_operand:OI 0 "s_register_operand" "=w") [(set (match_operand:OI 0 "s_register_operand" "=w")
(unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r")) (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD4_DUP))] UNSPEC_VLD4_DUP))]
"TARGET_NEON" "TARGET_NEON"
@ -5038,12 +5030,12 @@
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = gen_rtx_REG (DImode, regno + 6); ops[3] = gen_rtx_REG (DImode, regno + 6);
ops[4] = operands[1]; ops[4] = operands[1];
output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]", output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
ops); ops);
return ""; return "";
} }
else else
return "vld1.<V_sz_elem>\t%h0, [%1]"; return "vld1.<V_sz_elem>\t%h0, %A1";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
@ -5052,16 +5044,16 @@
) )
(define_insn "neon_vst4<mode>" (define_insn "neon_vst4<mode>"
[(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
(unspec:OI [(match_operand:OI 1 "s_register_operand" "w") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST4))] UNSPEC_VST4))]
"TARGET_NEON" "TARGET_NEON"
{ {
if (<V_sz_elem> == 64) if (<V_sz_elem> == 64)
return "vst1.64\t%h1, [%0]"; return "vst1.64\t%h1, %A0";
else else
return "vst4.<V_sz_elem>\t%h1, [%0]"; return "vst4.<V_sz_elem>\t%h1, %A0";
} }
[(set (attr "neon_type") [(set (attr "neon_type")
(if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
@ -5070,64 +5062,62 @@
) )
(define_expand "neon_vst4<mode>" (define_expand "neon_vst4<mode>"
[(match_operand:SI 0 "s_register_operand" "+r") [(match_operand:XI 0 "neon_struct_operand")
(match_operand:XI 1 "s_register_operand" "w") (match_operand:XI 1 "s_register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_NEON" "TARGET_NEON"
{ {
emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1])); rtx mem;
emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
mem = adjust_address (operands[0], OImode, 0);
emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
DONE; DONE;
}) })
(define_insn "neon_vst4qa<mode>" (define_insn "neon_vst4qa<mode>"
[(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
(unspec:OI [(match_operand:XI 2 "s_register_operand" "w") (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST4A)) UNSPEC_VST4A))]
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1)
(const_int 32)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[2]); int regno = REGNO (operands[1]);
rtx ops[5]; rtx ops[5];
ops[0] = operands[0]; ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno); ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 4); ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = gen_rtx_REG (DImode, regno + 8); ops[3] = gen_rtx_REG (DImode, regno + 8);
ops[4] = gen_rtx_REG (DImode, regno + 12); ops[4] = gen_rtx_REG (DImode, regno + 12);
output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops); output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
) )
(define_insn "neon_vst4qb<mode>" (define_insn "neon_vst4qb<mode>"
[(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
(unspec:OI [(match_operand:XI 2 "s_register_operand" "w") (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST4B)) UNSPEC_VST4B))]
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1)
(const_int 32)))]
"TARGET_NEON" "TARGET_NEON"
{ {
int regno = REGNO (operands[2]); int regno = REGNO (operands[1]);
rtx ops[5]; rtx ops[5];
ops[0] = operands[0]; ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno + 2); ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = gen_rtx_REG (DImode, regno + 6); ops[2] = gen_rtx_REG (DImode, regno + 6);
ops[3] = gen_rtx_REG (DImode, regno + 10); ops[3] = gen_rtx_REG (DImode, regno + 10);
ops[4] = gen_rtx_REG (DImode, regno + 14); ops[4] = gen_rtx_REG (DImode, regno + 14);
output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops); output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
return ""; return "";
} }
[(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
) )
(define_insn "neon_vst4_lane<mode>" (define_insn "neon_vst4_lane<mode>"
[(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
(unspec:<V_four_elem> (unspec:<V_four_elem>
[(match_operand:OI 1 "s_register_operand" "w") [(match_operand:OI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")
@ -5147,7 +5137,7 @@
ops[3] = gen_rtx_REG (DImode, regno + 4); ops[3] = gen_rtx_REG (DImode, regno + 4);
ops[4] = gen_rtx_REG (DImode, regno + 6); ops[4] = gen_rtx_REG (DImode, regno + 6);
ops[5] = operands[2]; ops[5] = operands[2];
output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
ops); ops);
return ""; return "";
} }
@ -5155,7 +5145,7 @@
) )
(define_insn "neon_vst4_lane<mode>" (define_insn "neon_vst4_lane<mode>"
[(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r")) [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
(unspec:<V_four_elem> (unspec:<V_four_elem>
[(match_operand:XI 1 "s_register_operand" "w") [(match_operand:XI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")
@ -5180,7 +5170,7 @@
ops[3] = gen_rtx_REG (DImode, regno + 8); ops[3] = gen_rtx_REG (DImode, regno + 8);
ops[4] = gen_rtx_REG (DImode, regno + 12); ops[4] = gen_rtx_REG (DImode, regno + 12);
ops[5] = GEN_INT (lane); ops[5] = GEN_INT (lane);
output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
ops); ops);
return ""; return "";
} }

4
gcc/config/arm/predicates.md
View File

@ -683,3 +683,7 @@
} }
return true; return true;
}) })
(define_special_predicate "neon_struct_operand"
(and (match_code "mem")
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))

6
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
* gcc.target/arm/neon-vld3-1.c: New test.
* gcc.target/arm/neon-vst3-1.c: New test.
* gcc.target/arm/neon/v*.c: Regenerate.
2011-04-12 Jakub Jelinek <jakub@redhat.com> 2011-04-12 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/48549 PR rtl-optimization/48549

27
gcc/testsuite/gcc.target/arm/neon-vld3-1.c Normal file
View File

@ -0,0 +1,27 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
uint32_t buffer[12];
void __attribute__((noinline))
foo (uint32_t *a)
{
uint32x4x3_t x;
x = vld3q_u32 (a);
x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
vst3q_u32 (a, x);
}
int
main (void)
{
buffer[0] = 1;
buffer[1] = 2;
foo (buffer);
return buffer[0] != 3;
}

25
gcc/testsuite/gcc.target/arm/neon-vst3-1.c Normal file
View File

@ -0,0 +1,25 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
uint32_t buffer[64];
void __attribute__((noinline))
foo (uint32_t *a)
{
uint32x4x3_t x;
x = vld3q_u32 (a);
a[35] = 1;
vst3q_lane_u32 (a + 32, x, 1);
}
int
main (void)
{
foo (buffer);
return buffer[35] != 1;
}

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupf32 (void)
out_float32x4_t = vld1q_dup_f32 (0); out_float32x4_t = vld1q_dup_f32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupp16 (void)
out_poly16x8_t = vld1q_dup_p16 (0); out_poly16x8_t = vld1q_dup_p16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupp8 (void)
out_poly8x16_t = vld1q_dup_p8 (0); out_poly8x16_t = vld1q_dup_p8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dups16 (void)
out_int16x8_t = vld1q_dup_s16 (0); out_int16x8_t = vld1q_dup_s16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dups32 (void)
out_int32x4_t = vld1q_dup_s32 (0); out_int32x4_t = vld1q_dup_s32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dups64 (void)
out_int64x2_t = vld1q_dup_s64 (0); out_int64x2_t = vld1q_dup_s64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dups8 (void)
out_int8x16_t = vld1q_dup_s8 (0); out_int8x16_t = vld1q_dup_s8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupu16 (void)
out_uint16x8_t = vld1q_dup_u16 (0); out_uint16x8_t = vld1q_dup_u16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupu32 (void)
out_uint32x4_t = vld1q_dup_u32 (0); out_uint32x4_t = vld1q_dup_u32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupu64 (void)
out_uint64x2_t = vld1q_dup_u64 (0); out_uint64x2_t = vld1q_dup_u64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
View File

@ -15,5 +15,5 @@ void test_vld1Q_dupu8 (void)
out_uint8x16_t = vld1q_dup_u8 (0); out_uint8x16_t = vld1q_dup_u8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanef32 (void)
out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanep16 (void)
out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanep8 (void)
out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanes16 (void)
out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanes32 (void)
out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanes64 (void)
out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_lanes8 (void)
out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_laneu16 (void)
out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_laneu32 (void)
out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_laneu64 (void)
out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
View File

@ -16,5 +16,5 @@ void test_vld1Q_laneu8 (void)
out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
View File

@ -15,5 +15,5 @@ void test_vld1Qf32 (void)
out_float32x4_t = vld1q_f32 (0); out_float32x4_t = vld1q_f32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
View File

@ -15,5 +15,5 @@ void test_vld1Qp16 (void)
out_poly16x8_t = vld1q_p16 (0); out_poly16x8_t = vld1q_p16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
View File

@ -15,5 +15,5 @@ void test_vld1Qp8 (void)
out_poly8x16_t = vld1q_p8 (0); out_poly8x16_t = vld1q_p8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
View File

@ -15,5 +15,5 @@ void test_vld1Qs16 (void)
out_int16x8_t = vld1q_s16 (0); out_int16x8_t = vld1q_s16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
View File

@ -15,5 +15,5 @@ void test_vld1Qs32 (void)
out_int32x4_t = vld1q_s32 (0); out_int32x4_t = vld1q_s32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
View File

@ -15,5 +15,5 @@ void test_vld1Qs64 (void)
out_int64x2_t = vld1q_s64 (0); out_int64x2_t = vld1q_s64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
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@ -15,5 +15,5 @@ void test_vld1Qs8 (void)
out_int8x16_t = vld1q_s8 (0); out_int8x16_t = vld1q_s8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
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@ -15,5 +15,5 @@ void test_vld1Qu16 (void)
out_uint16x8_t = vld1q_u16 (0); out_uint16x8_t = vld1q_u16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
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@ -15,5 +15,5 @@ void test_vld1Qu32 (void)
out_uint32x4_t = vld1q_u32 (0); out_uint32x4_t = vld1q_u32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
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@ -15,5 +15,5 @@ void test_vld1Qu64 (void)
out_uint64x2_t = vld1q_u64 (0); out_uint64x2_t = vld1q_u64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
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@ -15,5 +15,5 @@ void test_vld1Qu8 (void)
out_uint8x16_t = vld1q_u8 (0); out_uint8x16_t = vld1q_u8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
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@ -15,5 +15,5 @@ void test_vld1_dupf32 (void)
out_float32x2_t = vld1_dup_f32 (0); out_float32x2_t = vld1_dup_f32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
View File

@ -15,5 +15,5 @@ void test_vld1_dupp16 (void)
out_poly16x4_t = vld1_dup_p16 (0); out_poly16x4_t = vld1_dup_p16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
View File

@ -15,5 +15,5 @@ void test_vld1_dupp8 (void)
out_poly8x8_t = vld1_dup_p8 (0); out_poly8x8_t = vld1_dup_p8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
View File

@ -15,5 +15,5 @@ void test_vld1_dups16 (void)
out_int16x4_t = vld1_dup_s16 (0); out_int16x4_t = vld1_dup_s16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
View File

@ -15,5 +15,5 @@ void test_vld1_dups32 (void)
out_int32x2_t = vld1_dup_s32 (0); out_int32x2_t = vld1_dup_s32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
View File

@ -15,5 +15,5 @@ void test_vld1_dups64 (void)
out_int64x1_t = vld1_dup_s64 (0); out_int64x1_t = vld1_dup_s64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
View File

@ -15,5 +15,5 @@ void test_vld1_dups8 (void)
out_int8x8_t = vld1_dup_s8 (0); out_int8x8_t = vld1_dup_s8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
View File

@ -15,5 +15,5 @@ void test_vld1_dupu16 (void)
out_uint16x4_t = vld1_dup_u16 (0); out_uint16x4_t = vld1_dup_u16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
View File

@ -15,5 +15,5 @@ void test_vld1_dupu32 (void)
out_uint32x2_t = vld1_dup_u32 (0); out_uint32x2_t = vld1_dup_u32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
View File

@ -15,5 +15,5 @@ void test_vld1_dupu64 (void)
out_uint64x1_t = vld1_dup_u64 (0); out_uint64x1_t = vld1_dup_u64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
View File

@ -15,5 +15,5 @@ void test_vld1_dupu8 (void)
out_uint8x8_t = vld1_dup_u8 (0); out_uint8x8_t = vld1_dup_u8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanef32 (void)
out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanep16 (void)
out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanep8 (void)
out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanes16 (void)
out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanes32 (void)
out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanes64 (void)
out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
View File

@ -16,5 +16,5 @@ void test_vld1_lanes8 (void)
out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
View File

@ -16,5 +16,5 @@ void test_vld1_laneu16 (void)
out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
View File

@ -16,5 +16,5 @@ void test_vld1_laneu32 (void)
out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
View File

@ -16,5 +16,5 @@ void test_vld1_laneu64 (void)
out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
View File

@ -16,5 +16,5 @@ void test_vld1_laneu8 (void)
out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1f32.c
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@ -15,5 +15,5 @@ void test_vld1f32 (void)
out_float32x2_t = vld1_f32 (0); out_float32x2_t = vld1_f32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1p16.c
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@ -15,5 +15,5 @@ void test_vld1p16 (void)
out_poly16x4_t = vld1_p16 (0); out_poly16x4_t = vld1_p16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1p8.c
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@ -15,5 +15,5 @@ void test_vld1p8 (void)
out_poly8x8_t = vld1_p8 (0); out_poly8x8_t = vld1_p8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1s16.c
View File

@ -15,5 +15,5 @@ void test_vld1s16 (void)
out_int16x4_t = vld1_s16 (0); out_int16x4_t = vld1_s16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1s32.c
View File

@ -15,5 +15,5 @@ void test_vld1s32 (void)
out_int32x2_t = vld1_s32 (0); out_int32x2_t = vld1_s32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1s64.c
View File

@ -15,5 +15,5 @@ void test_vld1s64 (void)
out_int64x1_t = vld1_s64 (0); out_int64x1_t = vld1_s64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1s8.c
View File

@ -15,5 +15,5 @@ void test_vld1s8 (void)
out_int8x8_t = vld1_s8 (0); out_int8x8_t = vld1_s8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1u16.c
View File

@ -15,5 +15,5 @@ void test_vld1u16 (void)
out_uint16x4_t = vld1_u16 (0); out_uint16x4_t = vld1_u16 (0);
} }
/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1u32.c
View File

@ -15,5 +15,5 @@ void test_vld1u32 (void)
out_uint32x2_t = vld1_u32 (0); out_uint32x2_t = vld1_u32 (0);
} }
/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1u64.c
View File

@ -15,5 +15,5 @@ void test_vld1u64 (void)
out_uint64x1_t = vld1_u64 (0); out_uint64x1_t = vld1_u64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld1u8.c
View File

@ -15,5 +15,5 @@ void test_vld1u8 (void)
out_uint8x8_t = vld1_u8 (0); out_uint8x8_t = vld1_u8 (0);
} }
/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
View File

@ -16,5 +16,5 @@ void test_vld2Q_lanef32 (void)
out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
View File

@ -16,5 +16,5 @@ void test_vld2Q_lanep16 (void)
out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
View File

@ -16,5 +16,5 @@ void test_vld2Q_lanes16 (void)
out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
View File

@ -16,5 +16,5 @@ void test_vld2Q_lanes32 (void)
out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
View File

@ -16,5 +16,5 @@ void test_vld2Q_laneu16 (void)
out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
View File

@ -16,5 +16,5 @@ void test_vld2Q_laneu32 (void)
out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
View File

@ -15,6 +15,6 @@ void test_vld2Qf32 (void)
out_float32x4x2_t = vld2q_f32 (0); out_float32x4x2_t = vld2q_f32 (0);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
View File

@ -15,6 +15,6 @@ void test_vld2Qp16 (void)
out_poly16x8x2_t = vld2q_p16 (0); out_poly16x8x2_t = vld2q_p16 (0);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
View File

@ -15,6 +15,6 @@ void test_vld2Qp8 (void)
out_poly8x16x2_t = vld2q_p8 (0); out_poly8x16x2_t = vld2q_p8 (0);
} }
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
View File

@ -15,6 +15,6 @@ void test_vld2Qs16 (void)
out_int16x8x2_t = vld2q_s16 (0); out_int16x8x2_t = vld2q_s16 (0);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
View File

@ -15,6 +15,6 @@ void test_vld2Qs32 (void)
out_int32x4x2_t = vld2q_s32 (0); out_int32x4x2_t = vld2q_s32 (0);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
View File

@ -15,6 +15,6 @@ void test_vld2Qs8 (void)
out_int8x16x2_t = vld2q_s8 (0); out_int8x16x2_t = vld2q_s8 (0);
} }
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
View File

@ -15,6 +15,6 @@ void test_vld2Qu16 (void)
out_uint16x8x2_t = vld2q_u16 (0); out_uint16x8x2_t = vld2q_u16 (0);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
View File

@ -15,6 +15,6 @@ void test_vld2Qu32 (void)
out_uint32x4x2_t = vld2q_u32 (0); out_uint32x4x2_t = vld2q_u32 (0);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

4
gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
View File

@ -15,6 +15,6 @@ void test_vld2Qu8 (void)
out_uint8x16x2_t = vld2q_u8 (0); out_uint8x16x2_t = vld2q_u8 (0);
} }
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
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@ -15,5 +15,5 @@ void test_vld2_dupf32 (void)
out_float32x2x2_t = vld2_dup_f32 (0); out_float32x2x2_t = vld2_dup_f32 (0);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
View File

@ -15,5 +15,5 @@ void test_vld2_dupp16 (void)
out_poly16x4x2_t = vld2_dup_p16 (0); out_poly16x4x2_t = vld2_dup_p16 (0);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
View File

@ -15,5 +15,5 @@ void test_vld2_dupp8 (void)
out_poly8x8x2_t = vld2_dup_p8 (0); out_poly8x8x2_t = vld2_dup_p8 (0);
} }
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
View File

@ -15,5 +15,5 @@ void test_vld2_dups16 (void)
out_int16x4x2_t = vld2_dup_s16 (0); out_int16x4x2_t = vld2_dup_s16 (0);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
View File

@ -15,5 +15,5 @@ void test_vld2_dups32 (void)
out_int32x2x2_t = vld2_dup_s32 (0); out_int32x2x2_t = vld2_dup_s32 (0);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
View File

@ -15,5 +15,5 @@ void test_vld2_dups64 (void)
out_int64x1x2_t = vld2_dup_s64 (0); out_int64x1x2_t = vld2_dup_s64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
View File

@ -15,5 +15,5 @@ void test_vld2_dups8 (void)
out_int8x8x2_t = vld2_dup_s8 (0); out_int8x8x2_t = vld2_dup_s8 (0);
} }
/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
View File

@ -15,5 +15,5 @@ void test_vld2_dupu16 (void)
out_uint16x4x2_t = vld2_dup_u16 (0); out_uint16x4x2_t = vld2_dup_u16 (0);
} }
/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
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@ -15,5 +15,5 @@ void test_vld2_dupu32 (void)
out_uint32x2x2_t = vld2_dup_u32 (0); out_uint32x2x2_t = vld2_dup_u32 (0);
} }
/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
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@ -15,5 +15,5 @@ void test_vld2_dupu64 (void)
out_uint64x1x2_t = vld2_dup_u64 (0); out_uint64x1x2_t = vld2_dup_u64 (0);
} }
/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ /* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */ /* { dg-final { cleanup-saved-temps } } */

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