parent
98e5e08701
commit
630d42a0ae
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@ -3426,47 +3426,47 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
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adjust_address (operands[1], SImode, 4));
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adjust_address (operands[1], SImode, 4));
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return;
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return;
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}
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}
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else if (mode == DImode && TARGET_POWERPC64
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else if (mode == DImode && TARGET_POWERPC64
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == MEM && optimize > 0
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&& GET_CODE (operands[1]) == MEM && optimize > 0
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&& SLOW_UNALIGNED_ACCESS (DImode,
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&& SLOW_UNALIGNED_ACCESS (DImode,
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MEM_ALIGN (operands[1]) > 32
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MEM_ALIGN (operands[1]) > 32
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? 32
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? 32
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: MEM_ALIGN (operands[1]))
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: MEM_ALIGN (operands[1]))
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&& !no_new_pseudos)
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&& !no_new_pseudos)
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{
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rtx reg = gen_reg_rtx (SImode);
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emit_insn (gen_rtx_SET (SImode, reg,
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adjust_address (operands[1], SImode, 0)));
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reg = simplify_gen_subreg (DImode, reg, SImode, 0);
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emit_insn (gen_insvdi (operands[0], GEN_INT (32), const0_rtx, reg));
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reg = gen_reg_rtx (SImode);
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emit_insn (gen_rtx_SET (SImode, reg,
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adjust_address (operands[1], SImode, 4)));
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reg = simplify_gen_subreg (DImode, reg, SImode, 0);
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emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), reg));
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return;
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}
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else if (mode == DImode && TARGET_POWERPC64
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&& GET_CODE (operands[1]) == REG
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&& GET_CODE (operands[0]) == MEM && optimize > 0
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&& SLOW_UNALIGNED_ACCESS (DImode,
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MEM_ALIGN (operands[0]) > 32
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? 32
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: MEM_ALIGN (operands[0]))
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&& !no_new_pseudos)
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{
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{
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rtx reg = gen_reg_rtx (SImode);
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rtx reg = gen_reg_rtx (DImode);
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emit_insn (gen_rtx_SET (SImode, reg,
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emit_move_insn (reg,
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adjust_address (operands[1], SImode, 0)));
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reg = simplify_gen_subreg (DImode, reg, SImode, 0);
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emit_insn (gen_insvdi (operands[0], GEN_INT (32), const0_rtx, reg));
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reg = gen_reg_rtx (SImode);
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emit_insn (gen_rtx_SET (SImode, reg,
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adjust_address (operands[1], SImode, 4)));
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reg = simplify_gen_subreg (DImode, reg, SImode, 0);
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emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), reg));
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return;
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}
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else if (mode == DImode && TARGET_POWERPC64
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&& GET_CODE (operands[1]) == REG
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&& GET_CODE (operands[0]) == MEM && optimize > 0
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&& SLOW_UNALIGNED_ACCESS (DImode,
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MEM_ALIGN (operands[0]) > 32
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? 32
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: MEM_ALIGN (operands[0]))
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&& !no_new_pseudos)
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{
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rtx reg = gen_reg_rtx (DImode);
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emit_move_insn (reg,
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gen_rtx_LSHIFTRT (DImode, operands[1], GEN_INT (32)));
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gen_rtx_LSHIFTRT (DImode, operands[1], GEN_INT (32)));
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emit_move_insn (adjust_address (operands[0], SImode, 0),
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emit_move_insn (adjust_address (operands[0], SImode, 0),
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simplify_gen_subreg (SImode, reg, DImode, 0));
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simplify_gen_subreg (SImode, reg, DImode, 0));
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emit_move_insn (reg, operands[1]);
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emit_move_insn (reg, operands[1]);
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emit_move_insn (adjust_address (operands[0], SImode, 4),
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emit_move_insn (adjust_address (operands[0], SImode, 4),
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simplify_gen_subreg (SImode, reg, DImode, 0));
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simplify_gen_subreg (SImode, reg, DImode, 0));
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return;
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return;
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}
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}
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if (!no_new_pseudos)
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if (!no_new_pseudos)
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{
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{
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if (GET_CODE (operands[1]) == MEM && optimize > 0
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if (GET_CODE (operands[1]) == MEM && optimize > 0
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