pa.md (indexing loads and stores): Provide variants which avoid reload problems with shift-add operations.
* pa.md (indexing loads and stores): Provide variants which avoid reload problems with shift-add operations. From-SVN: r5793
This commit is contained in:
Jeff Law
parent
51b8cba126
commit
6358b911d4
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@ -979,6 +979,27 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "&=r")
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(mem:SI (plus:SI (plus:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rI"))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh2add %1,%2,%0\;ldw %3(0,%0),%0\";
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else
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return \"sh2add %1,%2,%0\;ldwx %3(0,%0),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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;; Load or store with base-register modification.
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(define_insn "pre_ldwm"
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@ -1186,6 +1207,27 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=&r")
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(mem:HI (plus:SI (plus:SI
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(mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rI"))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh1add %2,%1,%0\;ldh %3(0,%0),%0\";
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else
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return \"sh1add %2,%1,%0\;ldhx %3(0,%0),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:HI 3 "register_operand" "=r")
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(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "0")
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@ -1380,6 +1422,30 @@
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[(set_attr "type" "fpload")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Ugh. Output is a FP register; so we need to earlyclobber something
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;; else as a temporary.
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=fx")
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(mem:DF (plus:SI
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(plus:SI
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(mult:SI (match_operand:SI 1 "register_operand" "+&r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rL"))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh3add %1,%2,%1\;fldds %3(0,%1),%0\";
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else
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return \"sh3add %1,%2,%1\;flddx %3(0,%1),%0\";
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}"
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[(set_attr "type" "fpload")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 8))
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@ -1390,6 +1456,30 @@
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[(set_attr "type" "fpstore")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Ugh. Output is a FP register; so we need to earlyclobber something
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;; else as a temporary.
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(define_insn ""
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[(set (mem:DF (plus:SI
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(plus:SI
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(mult:SI (match_operand:SI 1 "register_operand" "+&r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rL")))
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(match_operand:DF 0 "register_operand" "=fx"))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh3add %1,%2,%1\;fstds %3(0,%1),%0\";
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else
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return \"sh3add %1,%2,%1\;fstdx %3(0,%1),%0\";
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}"
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[(set_attr "type" "fpstore")
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(set_attr "length" "8")])
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(define_expand "movdi"
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[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
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(match_operand:DI 1 "general_operand" ""))]
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@ -1562,6 +1652,30 @@
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[(set_attr "type" "fpload")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Ugh. Output is a FP register; so we need to earlyclobber something
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;; else as a temporary.
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=fx")
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(mem:SF (plus:SI
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(plus:SI
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(mult:SI (match_operand:SI 1 "register_operand" "+&r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rL"))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh2add %1,%2,%1\;fldws %3(0,%1),%0\";
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else
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return \"sh2add %1,%2,%1\;fldwx %3(0,%1),%0\";
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}"
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[(set_attr "type" "fpload")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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@ -1571,6 +1685,30 @@
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"fstwx,s %0,%1(0,%2)"
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[(set_attr "type" "fpstore")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Ugh. Output is a FP register; so we need to earlyclobber something
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;; else as a temporary.
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(define_insn ""
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[(set (mem:SF (plus:SI
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(plus:SI
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(mult:SI (match_operand:SI 1 "register_operand" "+&r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rL")))
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(match_operand:SF 0 "register_operand" "=fx"))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh2add %1,%2,%1\;fstds %3(0,%1),%0\";
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else
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return \"sh2add %1,%2,%1\;fstdx %3(0,%1),%0\";
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}"
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[(set_attr "type" "fpstore")
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(set_attr "length" "8")])
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;;- zero extension instructions
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@ -2392,7 +2530,7 @@
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;; This variant of the above insn can occur if the first operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize them while reloading.
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;; seem to be a way around it. Only recognize it while reloading.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=&r")
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