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arm: Add support for Neoverse N2 CPU

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This adds support for Arm's Neoverse N2 CPU to the AArch32 backend.
Neoverse N2 builds AArch32 at EL0 and therefore needs support in AArch32
GCC.

gcc/ChangeLog:

	* config/arm/arm-cpus.in (neoverse-n2): New.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* doc/invoke.texi: Document support for Neoverse N2.
This commit is contained in:
Alex Coplan 2020-09-24 17:22:44 +01:00
parent 50d9db203b
commit 637ad78cdf
4 changed files with 21 additions and 6 deletions
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11
gcc/config/arm/arm-cpus.in
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@ -1459,6 +1459,17 @@ begin cpu neoverse-n1
part d0c
end cpu neoverse-n1
begin cpu neoverse-n2
cname neoversen2
tune for cortex-a57
tune flags LDSCHED
architecture armv8.5-a+fp16+bf16+i8mm
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
vendor 41
part 0xd49
end cpu neoverse-n2
# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations
begin cpu cortex-a75.cortex-a55
cname cortexa75cortexa55

3
gcc/config/arm/arm-tables.opt
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@ -243,6 +243,9 @@ Enum(processor_type) String(cortex-a77) Value( TARGET_CPU_cortexa77)
EnumValue
Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
EnumValue
Enum(processor_type) String(neoverse-n2) Value( TARGET_CPU_neoversen2)
EnumValue
Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55)

7
gcc/config/arm/arm-tune.md
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@ -45,7 +45,8 @@
cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
cortexa73cortexa53,cortexa55,cortexa75,
cortexa76,cortexa76ae,cortexa77,
neoversen1,cortexa75cortexa55,cortexa76cortexa55,
neoversev1,cortexm23,cortexm33,
cortexm35p,cortexm55,cortexr52"
neoversen1,neoversen2,cortexa75cortexa55,
cortexa76cortexa55,neoversev1,cortexm23,
cortexm33,cortexm35p,cortexm55,
cortexr52"
(const (symbol_ref "((enum attr_tune) arm_tune)")))

6
gcc/doc/invoke.texi
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@ -19385,9 +19385,9 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
@samp{cortex-m35p}, @samp{cortex-m55},
@samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
@samp{neoverse-n1}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt},
@samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te},
@samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are: