re PR bootstrap/49964 (Bootstrap failed with AVX turned on)
PR target/49964 * config/i386/i386.c (ix86_expand_call): Don't create nested PARALLELs for TARGET_VZEROUPPER. (ix86_split_call_vzeroupper): Fix extraction of the original call. * config/i386/i386.md (*call_rex64_ms_sysv_vzeroupper): Don't recognize nested PARALLELs. (*call_pop_vzeroupper, *sibcall_pop_vzeroupper, *call_value_rex64_ms_sysv_vzeroupper, *call_value_pop_vzeroupper, *sibcall_value_pop_vzeroupper): Likewise. From-SVN: r177408
This commit is contained in:
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276e7ed024
commit
6394830f47
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@ -1,3 +1,15 @@
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2011-08-04 Richard Henderson <rth@redhat.com>
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PR target/49964
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* config/i386/i386.c (ix86_expand_call): Don't create nested
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PARALLELs for TARGET_VZEROUPPER.
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(ix86_split_call_vzeroupper): Fix extraction of the original call.
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* config/i386/i386.md (*call_rex64_ms_sysv_vzeroupper): Don't
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recognize nested PARALLELs.
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(*call_pop_vzeroupper, *sibcall_pop_vzeroupper,
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*call_value_rex64_ms_sysv_vzeroupper, *call_value_pop_vzeroupper,
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*sibcall_value_pop_vzeroupper): Likewise.
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2011-08-04 Richard Henderson <rth@redhat.com>
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PR middle-end/49968
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@ -21501,7 +21501,17 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
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rtx callarg2,
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rtx pop, bool sibcall)
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{
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/* We need to represent that SI and DI registers are clobbered
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by SYSV calls. */
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static int clobbered_registers[] = {
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XMM6_REG, XMM7_REG, XMM8_REG,
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XMM9_REG, XMM10_REG, XMM11_REG,
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XMM12_REG, XMM13_REG, XMM14_REG,
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XMM15_REG, SI_REG, DI_REG
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};
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rtx vec[ARRAY_SIZE (clobbered_registers) + 3];
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rtx use = NULL, call;
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unsigned int vec_len;
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if (pop == const0_rtx)
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pop = NULL;
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@ -21545,52 +21555,40 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
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fnaddr = gen_rtx_MEM (QImode, copy_to_mode_reg (Pmode, fnaddr));
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}
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vec_len = 0;
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call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
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if (retval)
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call = gen_rtx_SET (VOIDmode, retval, call);
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vec[vec_len++] = call;
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if (pop)
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{
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pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
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pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
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call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
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vec[vec_len++] = pop;
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}
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if (TARGET_64BIT_MS_ABI
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&& (!callarg2 || INTVAL (callarg2) != -2))
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{
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/* We need to represent that SI and DI registers are clobbered
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by SYSV calls. */
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static int clobbered_registers[] = {
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XMM6_REG, XMM7_REG, XMM8_REG,
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XMM9_REG, XMM10_REG, XMM11_REG,
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XMM12_REG, XMM13_REG, XMM14_REG,
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XMM15_REG, SI_REG, DI_REG
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};
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unsigned int i;
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rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
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rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
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UNSPEC_MS_TO_SYSV_CALL);
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unsigned i;
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vec[vec_len++] = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
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UNSPEC_MS_TO_SYSV_CALL);
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vec[0] = call;
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vec[1] = unspec;
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for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
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vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
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? TImode : DImode,
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gen_rtx_REG
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(SSE_REGNO_P (clobbered_registers[i])
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? TImode : DImode,
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clobbered_registers[i]));
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call = gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
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+ 2, vec));
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vec[vec_len++]
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= gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
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? TImode : DImode,
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gen_rtx_REG (SSE_REGNO_P (clobbered_registers[i])
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? TImode : DImode,
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clobbered_registers[i]));
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}
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/* Add UNSPEC_CALL_NEEDS_VZEROUPPER decoration. */
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if (TARGET_VZEROUPPER)
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{
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rtx unspec;
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int avx256;
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if (cfun->machine->callee_pass_avx256_p)
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{
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if (cfun->machine->callee_return_avx256_p)
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@ -21606,15 +21604,13 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
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if (reload_completed)
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emit_insn (gen_avx_vzeroupper (GEN_INT (avx256)));
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else
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{
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unspec = gen_rtx_UNSPEC (VOIDmode,
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gen_rtvec (1, GEN_INT (avx256)),
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UNSPEC_CALL_NEEDS_VZEROUPPER);
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call = gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (2, call, unspec));
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}
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vec[vec_len++] = gen_rtx_UNSPEC (VOIDmode,
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gen_rtvec (1, GEN_INT (avx256)),
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UNSPEC_CALL_NEEDS_VZEROUPPER);
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}
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if (vec_len > 1)
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call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (vec_len, vec));
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call = emit_call_insn (call);
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if (use)
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CALL_INSN_FUNCTION_USAGE (call) = use;
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@ -21625,9 +21621,20 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
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void
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ix86_split_call_vzeroupper (rtx insn, rtx vzeroupper)
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{
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rtx call = XVECEXP (PATTERN (insn), 0, 0);
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rtx pat = PATTERN (insn);
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rtvec vec = XVEC (pat, 0);
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int len = GET_NUM_ELEM (vec) - 1;
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/* Strip off the last entry of the parallel. */
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gcc_assert (GET_CODE (RTVEC_ELT (vec, len)) == UNSPEC);
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gcc_assert (XINT (RTVEC_ELT (vec, len), 1) == UNSPEC_CALL_NEEDS_VZEROUPPER);
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if (len == 1)
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pat = RTVEC_ELT (vec, 0);
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else
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pat = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (len, &RTVEC_ELT (vec, 0)));
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emit_insn (gen_avx_vzeroupper (vzeroupper));
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emit_call_insn (call);
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emit_call_insn (pat);
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}
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/* Output the assembly for a call instruction. */
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@ -11050,22 +11050,21 @@
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[(set_attr "type" "call")])
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(define_insn_and_split "*call_rex64_ms_sysv_vzeroupper"
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[(parallel
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[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
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(match_operand 1 "" ""))
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(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
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(clobber (reg:TI XMM6_REG))
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(clobber (reg:TI XMM7_REG))
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(clobber (reg:TI XMM8_REG))
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(clobber (reg:TI XMM9_REG))
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(clobber (reg:TI XMM10_REG))
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(clobber (reg:TI XMM11_REG))
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(clobber (reg:TI XMM12_REG))
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(clobber (reg:TI XMM13_REG))
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(clobber (reg:TI XMM14_REG))
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(clobber (reg:TI XMM15_REG))
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(clobber (reg:DI SI_REG))
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(clobber (reg:DI DI_REG))])
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[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
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(match_operand 1 "" ""))
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(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
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(clobber (reg:TI XMM6_REG))
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(clobber (reg:TI XMM7_REG))
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(clobber (reg:TI XMM8_REG))
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(clobber (reg:TI XMM9_REG))
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(clobber (reg:TI XMM10_REG))
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(clobber (reg:TI XMM11_REG))
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(clobber (reg:TI XMM12_REG))
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(clobber (reg:TI XMM13_REG))
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(clobber (reg:TI XMM14_REG))
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(clobber (reg:TI XMM15_REG))
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(clobber (reg:DI SI_REG))
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(clobber (reg:DI DI_REG))
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(unspec [(match_operand 2 "const_int_operand" "")]
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UNSPEC_CALL_NEEDS_VZEROUPPER)]
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"TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
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@ -11128,12 +11127,11 @@
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})
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(define_insn_and_split "*call_pop_vzeroupper"
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[(parallel
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[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
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(match_operand:SI 1 "" ""))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 2 "immediate_operand" "i")))])
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[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
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(match_operand:SI 1 "" ""))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 2 "immediate_operand" "i")))
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(unspec [(match_operand 3 "const_int_operand" "")]
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UNSPEC_CALL_NEEDS_VZEROUPPER)]
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"TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
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@ -11154,12 +11152,11 @@
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[(set_attr "type" "call")])
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(define_insn_and_split "*sibcall_pop_vzeroupper"
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[(parallel
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[(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
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(match_operand 1 "" ""))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 2 "immediate_operand" "i")))])
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[(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
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(match_operand 1 "" ""))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 2 "immediate_operand" "i")))
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(unspec [(match_operand 3 "const_int_operand" "")]
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UNSPEC_CALL_NEEDS_VZEROUPPER)]
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"TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
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@ -11248,23 +11245,22 @@
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[(set_attr "type" "callv")])
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(define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper"
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[(parallel
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
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(match_operand 2 "" "")))
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(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
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(clobber (reg:TI XMM6_REG))
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(clobber (reg:TI XMM7_REG))
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(clobber (reg:TI XMM8_REG))
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(clobber (reg:TI XMM9_REG))
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(clobber (reg:TI XMM10_REG))
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(clobber (reg:TI XMM11_REG))
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(clobber (reg:TI XMM12_REG))
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(clobber (reg:TI XMM13_REG))
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(clobber (reg:TI XMM14_REG))
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(clobber (reg:TI XMM15_REG))
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(clobber (reg:DI SI_REG))
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(clobber (reg:DI DI_REG))])
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
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(match_operand 2 "" "")))
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(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
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(clobber (reg:TI XMM6_REG))
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(clobber (reg:TI XMM7_REG))
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(clobber (reg:TI XMM8_REG))
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(clobber (reg:TI XMM9_REG))
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(clobber (reg:TI XMM10_REG))
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(clobber (reg:TI XMM11_REG))
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(clobber (reg:TI XMM12_REG))
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(clobber (reg:TI XMM13_REG))
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(clobber (reg:TI XMM14_REG))
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(clobber (reg:TI XMM15_REG))
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(clobber (reg:DI SI_REG))
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(clobber (reg:DI DI_REG))
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(unspec [(match_operand 3 "const_int_operand" "")]
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UNSPEC_CALL_NEEDS_VZEROUPPER)]
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"TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
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@ -11310,13 +11306,12 @@
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})
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(define_insn_and_split "*call_value_pop_vzeroupper"
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[(parallel
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
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(match_operand 2 "" "")))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))])
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
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(match_operand 2 "" "")))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))
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(unspec [(match_operand 4 "const_int_operand" "")]
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UNSPEC_CALL_NEEDS_VZEROUPPER)]
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"TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
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@ -11338,13 +11333,12 @@
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[(set_attr "type" "callv")])
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(define_insn_and_split "*sibcall_value_pop_vzeroupper"
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[(parallel
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
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(match_operand 2 "" "")))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))])
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
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(match_operand 2 "" "")))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))
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(unspec [(match_operand 4 "const_int_operand" "")]
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UNSPEC_CALL_NEEDS_VZEROUPPER)]
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"TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
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