pdp11.md: Use iterators.
* config/pdp11/pdp11.md: Use iterators. (addqi3, subqi3, iorsi3, xorsi3): Delete. From-SVN: r166148
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@ -1,3 +1,8 @@
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2010-11-01 Paul Koning <ni1d@arrl.net>
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* config/pdp11/pdp11.md: Use iterators.
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* config/pdp11/pdp11.md (addqi3, subqi3, iorsi3, xorsi3): Delete.
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2010-11-01 Steve Ellcey <sje@cup.hp.com>
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* defaults.h (TARGET_VTABLE_USES_DESCRIPTORS): Move under ifdef
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@ -122,35 +122,20 @@
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}"
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[(set_attr "length" "4,4,6,6,12")])
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(define_insn "*cmphi"
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(define_insn "*cmp<mode>"
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[(set (cc0)
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(compare (match_operand:HI 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
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(match_operand:HI 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
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(compare (match_operand:PDPint 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
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(match_operand:PDPint 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
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""
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"@
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tst %0
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cmp %0,%1
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cmp %0,%1
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tst %0
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cmp %0,%1
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cmp %0,%1"
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tst<PDPint:isfx> %0
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cmp<PDPint:isfx> %0,%1
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cmp<PDPint:isfx> %0,%1
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tst<PDPint:isfx> %0
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cmp<PDPint:isfx> %0,%1
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cmp<PDPint:isfx> %0,%1"
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[(set_attr "length" "2,2,4,4,4,6")])
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(define_insn "*cmpqi"
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[(set (cc0)
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(compare (match_operand:QI 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
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(match_operand:QI 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
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""
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"@
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tstb %0
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cmpb %0,%1
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cmpb %0,%1
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tstb %0
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cmpb %0,%1
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cmpb %0,%1"
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[(set_attr "length" "2,2,4,4,4,6")])
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;; sob instruction - we need an assembler which can make this instruction
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;; valid under _all_ circumstances!
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@ -211,22 +196,10 @@
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"TARGET_FPU"
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"")
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(define_expand "cbranchhi4"
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(define_expand "cbranch<mode>4"
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[(set (cc0)
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(compare (match_operand:HI 1 "general_operand")
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(match_operand:HI 2 "general_operand")))
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(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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""
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"")
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(define_expand "cbranchqi4"
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[(set (cc0)
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(compare (match_operand:QI 1 "general_operand")
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(match_operand:QI 2 "general_operand")))
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(compare (match_operand:PDPint 1 "general_operand")
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(match_operand:PDPint 2 "general_operand")))
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(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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@ -298,29 +271,16 @@
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;; we could split it up and make several sub-cases...
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[(set_attr "length" "4,6,8,16,16")])
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(define_insn "movhi"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(match_operand:HI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
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(define_insn "mov<mode>"
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[(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(match_operand:PDPint 1 "general_operand" "rRN,Qi,rRN,Qi"))]
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""
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"*
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{
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if (operands[1] == const0_rtx)
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return \"clr %0\";
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return \"clr<PDPint:isfx> %0\";
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return \"mov %1, %0\";
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}"
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[(set_attr "length" "2,4,4,6")])
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(define_insn "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
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""
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"*
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{
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if (operands[1] == const0_rtx)
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return \"clrb %0\";
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return \"movb %1, %0\";
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return \"mov<PDPint:isfx> %1, %0\";
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}"
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[(set_attr "length" "2,4,4,6")])
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@ -718,25 +678,6 @@
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}"
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[(set_attr "length" "2,4,4,6")])
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(define_insn "addqi3"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
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(match_operand:QI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
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""
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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if (INTVAL(operands[2]) == 1)
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return \"incb %0\";
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else if (INTVAL(operands[2]) == -1)
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return \"decb %0\";
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}
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return \"add %2, %0\";
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}"
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[(set_attr "length" "2,4,4,6")])
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;;- subtract instructions
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;; we don't have to care for constant second
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@ -798,19 +739,6 @@
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}"
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[(set_attr "length" "2,4,4,6")])
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(define_insn "subqi3"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
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(match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
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""
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"*
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{
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gcc_assert (GET_CODE (operands[2]) != CONST_INT);
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return \"sub %2, %0\";
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}"
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[(set_attr "length" "2,4,4,6")])
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;;;;- and instructions
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;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn.
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[(set_attr "length" "2,4,4,6")])
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;;- Bit set (inclusive or) instructions
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(define_insn "iorsi3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,o,o,r,r,r,o,o,o")
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(ior:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
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(match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
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(define_insn "ior<mode>3"
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[(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(ior:PDPint (match_operand:PDPint 1 "general_operand" "%0,0,0,0")
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(match_operand:PDPint 2 "general_operand" "rR,Qi,rR,Qi")))]
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""
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"*
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{ /* Here we trust that operands don't overlap
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or is lateoperands the low word?? - looks like it! */
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rtx lateoperands[3];
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lateoperands[0] = operands[0];
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if (REG_P (operands[0]))
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operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
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else
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operands[0] = adjust_address (operands[0], HImode, 2);
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if (! CONSTANT_P(operands[2]))
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{
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lateoperands[2] = operands[2];
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if (REG_P (operands[2]))
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operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
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else
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operands[2] = adjust_address (operands[2], HImode, 2);
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output_asm_insn (\"bis %2, %0\", operands);
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output_asm_insn (\"bis %2, %0\", lateoperands);
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return \"\";
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}
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lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
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operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
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/* these have different lengths, so we should have
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different constraints! */
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if (INTVAL(operands[2]))
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output_asm_insn (\"bis %2, %0\", operands);
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if (INTVAL(lateoperands[2]))
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output_asm_insn (\"bis %2, %0\", lateoperands);
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return \"\";
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}"
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[(set_attr "length" "4,8,8,12,4,4,8,6,6,12")])
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(define_insn "iorhi3"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(ior:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
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(match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
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""
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"bis %2, %0"
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"bis<PDPint:isfx> %2, %0"
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[(set_attr "length" "2,4,4,6")])
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(define_insn "iorqi3"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q")
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(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
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(match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
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""
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"bisb %2, %0")
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;;- xor instructions
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(xor:SI (match_operand:SI 1 "register_operand" "%0")
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_40_PLUS"
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"*
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{ /* Here we trust that operands don't overlap */
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rtx lateoperands[3];
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lateoperands[0] = operands[0];
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operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
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if (REG_P(operands[2]))
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{
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lateoperands[2] = operands[2];
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operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
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output_asm_insn (\"xor %2, %0\", operands);
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output_asm_insn (\"xor %2, %0\", lateoperands);
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}
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return \"\";
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}"
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[(set_attr "length" "4")])
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(define_insn "xorhi3"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q")
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(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
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;;- one complement instructions
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(define_insn "one_cmplhi2"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q")
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(not:HI (match_operand:HI 1 "general_operand" "0,0")))]
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(define_insn "one_cmpl<mode>2"
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[(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,Q")
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(not:PDPint (match_operand:PDPint 1 "general_operand" "0,0")))]
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""
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"com %0"
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[(set_attr "length" "2,4")])
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(define_insn "one_cmplqi2"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR")
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(not:QI (match_operand:QI 1 "general_operand" "0,g")))]
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""
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"@
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comb %0
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movb %1, %0\; comb %0"
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"com<PDPint:isfx> %0"
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[(set_attr "length" "2,4")])
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;;- arithmetic shift instructions
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