[AArch64] Use atomic load-operate instructions for fetch-update patterns.
gcc/ 2015-09-22 Matthew Wahab <matthew.wahab@arm.com> * config/aarch64/aarch64-protos.h (aarch64_atomic_ldop_supported_p): Declare. * config/aarch64/aarch64.c (aarch64_atomic_ldop_supported_p): New. (enum aarch64_atomic_load_op_code): New. (aarch64_emit_atomic_load_op): New. (aarch64_gen_atomic_ldop): Update to support load-operate patterns. * config/aarch64/atomics.md (atomic_<atomic_optab><mode>): Change to an expander. (aarch64_atomic_<atomic_optab><mode>): New. (aarch64_atomic_<atomic_optab><mode>_lse): New. (atomic_fetch_<atomic_optab><mode>): Change to an expander. (aarch64_atomic_fetch_<atomic_optab><mode>): New. (aarch64_atomic_fetch_<atomic_optab><mode>_lse): New. gcc/testsuite/ 2015-09-22 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/aarch64/atomic-inst-ldadd.c: New. * gcc.target/aarch64/atomic-inst-ldlogic.c: New. From-SVN: r228001
This commit is contained in:
Matthew Wahab
Matthew Wahab
parent
6380d2bc38
commit
641c2f8b69
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@ -1,3 +1,20 @@
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* config/aarch64/aarch64-protos.h
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(aarch64_atomic_ldop_supported_p): Declare.
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* config/aarch64/aarch64.c (aarch64_atomic_ldop_supported_p): New.
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(enum aarch64_atomic_load_op_code): New.
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(aarch64_emit_atomic_load_op): New.
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(aarch64_gen_atomic_ldop): Update to support load-operate
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patterns.
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* config/aarch64/atomics.md (atomic_<atomic_optab><mode>): Change
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to an expander.
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(aarch64_atomic_<atomic_optab><mode>): New.
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(aarch64_atomic_<atomic_optab><mode>_lse): New.
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(atomic_fetch_<atomic_optab><mode>): Change to an expander.
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(aarch64_atomic_fetch_<atomic_optab><mode>): New.
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(aarch64_atomic_fetch_<atomic_optab><mode>_lse): New.
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* config/aarch64/aarch64/atomics.md (UNSPECV_ATOMIC_LDOP): New.
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@ -378,6 +378,8 @@ rtx aarch64_load_tp (rtx);
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void aarch64_expand_compare_and_swap (rtx op[]);
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void aarch64_split_compare_and_swap (rtx op[]);
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void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
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bool aarch64_atomic_ldop_supported_p (enum rtx_code);
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void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx);
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void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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@ -10871,6 +10871,32 @@ aarch64_expand_compare_and_swap (rtx operands[])
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emit_insn (gen_rtx_SET (bval, x));
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}
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/* Test whether the target supports using a atomic load-operate instruction.
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CODE is the operation and AFTER is TRUE if the data in memory after the
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operation should be returned and FALSE if the data before the operation
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should be returned. Returns FALSE if the operation isn't supported by the
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architecture. */
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bool
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aarch64_atomic_ldop_supported_p (enum rtx_code code)
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{
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if (!TARGET_LSE)
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return false;
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switch (code)
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{
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case SET:
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case AND:
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case IOR:
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case XOR:
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case MINUS:
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case PLUS:
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return true;
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default:
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return false;
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}
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}
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/* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
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sequence implementing an atomic operation. */
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@ -11013,26 +11039,169 @@ aarch64_emit_atomic_swap (machine_mode mode, rtx dst, rtx value,
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emit_insn (gen (dst, mem, value, model));
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}
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/* Emit an atomic operation where the architecture supports it. */
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/* Operations supported by aarch64_emit_atomic_load_op. */
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enum aarch64_atomic_load_op_code
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{
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AARCH64_LDOP_PLUS, /* A + B */
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AARCH64_LDOP_XOR, /* A ^ B */
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AARCH64_LDOP_OR, /* A | B */
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AARCH64_LDOP_BIC /* A & ~B */
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};
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/* Emit an atomic load-operate. */
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static void
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aarch64_emit_atomic_load_op (enum aarch64_atomic_load_op_code code,
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machine_mode mode, rtx dst, rtx src,
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rtx mem, rtx model)
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{
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typedef rtx (*aarch64_atomic_load_op_fn) (rtx, rtx, rtx, rtx);
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const aarch64_atomic_load_op_fn plus[] =
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{
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gen_aarch64_atomic_loadaddqi,
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gen_aarch64_atomic_loadaddhi,
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gen_aarch64_atomic_loadaddsi,
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gen_aarch64_atomic_loadadddi
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};
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const aarch64_atomic_load_op_fn eor[] =
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{
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gen_aarch64_atomic_loadeorqi,
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gen_aarch64_atomic_loadeorhi,
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gen_aarch64_atomic_loadeorsi,
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gen_aarch64_atomic_loadeordi
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};
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const aarch64_atomic_load_op_fn ior[] =
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{
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gen_aarch64_atomic_loadsetqi,
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gen_aarch64_atomic_loadsethi,
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gen_aarch64_atomic_loadsetsi,
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gen_aarch64_atomic_loadsetdi
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};
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const aarch64_atomic_load_op_fn bic[] =
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{
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gen_aarch64_atomic_loadclrqi,
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gen_aarch64_atomic_loadclrhi,
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gen_aarch64_atomic_loadclrsi,
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gen_aarch64_atomic_loadclrdi
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};
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aarch64_atomic_load_op_fn gen;
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int idx = 0;
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switch (mode)
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{
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case QImode: idx = 0; break;
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case HImode: idx = 1; break;
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case SImode: idx = 2; break;
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case DImode: idx = 3; break;
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default:
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gcc_unreachable ();
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}
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switch (code)
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{
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case AARCH64_LDOP_PLUS: gen = plus[idx]; break;
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case AARCH64_LDOP_XOR: gen = eor[idx]; break;
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case AARCH64_LDOP_OR: gen = ior[idx]; break;
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case AARCH64_LDOP_BIC: gen = bic[idx]; break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen (dst, mem, src, model));
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}
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/* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
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location to store the data read from memory. MEM is the memory location to
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read and modify. MODEL_RTX is the memory ordering to use. VALUE is the
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second operand for the operation. Either OUT_DATA or OUT_RESULT, but not
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both, can be NULL. */
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void
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aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data,
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rtx mem, rtx value, rtx model_rtx)
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{
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machine_mode mode = GET_MODE (mem);
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machine_mode wmode = (mode == DImode ? DImode : SImode);
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const bool short_mode = (mode < SImode);
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aarch64_atomic_load_op_code ldop_code;
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rtx src;
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rtx x;
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out_data = gen_lowpart (mode, out_data);
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if (out_data)
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out_data = gen_lowpart (mode, out_data);
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/* Make sure the value is in a register, putting it into a destination
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register if it needs to be manipulated. */
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if (!register_operand (value, mode)
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|| code == AND || code == MINUS)
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{
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src = out_data;
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emit_move_insn (src, gen_lowpart (mode, value));
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}
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else
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src = value;
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gcc_assert (register_operand (src, mode));
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/* Preprocess the data for the operation as necessary. If the operation is
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a SET then emit a swap instruction and finish. */
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switch (code)
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{
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case SET:
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aarch64_emit_atomic_swap (mode, out_data, value, mem, model_rtx);
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aarch64_emit_atomic_swap (mode, out_data, src, mem, model_rtx);
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return;
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case MINUS:
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/* Negate the value and treat it as a PLUS. */
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{
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rtx neg_src;
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/* Resize the value if necessary. */
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if (short_mode)
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src = gen_lowpart (wmode, src);
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neg_src = gen_rtx_NEG (wmode, src);
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emit_insn (gen_rtx_SET (src, neg_src));
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if (short_mode)
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src = gen_lowpart (mode, src);
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}
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/* Fall-through. */
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case PLUS:
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ldop_code = AARCH64_LDOP_PLUS;
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break;
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case IOR:
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ldop_code = AARCH64_LDOP_OR;
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break;
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case XOR:
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ldop_code = AARCH64_LDOP_XOR;
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break;
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case AND:
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{
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rtx not_src;
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/* Resize the value if necessary. */
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if (short_mode)
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src = gen_lowpart (wmode, src);
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not_src = gen_rtx_NOT (wmode, src);
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emit_insn (gen_rtx_SET (src, not_src));
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if (short_mode)
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src = gen_lowpart (mode, src);
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}
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ldop_code = AARCH64_LDOP_BIC;
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break;
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default:
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/* The operation can't be done with atomic instructions. */
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gcc_unreachable ();
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}
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aarch64_emit_atomic_load_op (ldop_code, mode, out_data, src, mem, model_rtx);
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}
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/* Split an atomic operation. */
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@ -225,16 +225,37 @@
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}
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)
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(define_insn_and_split "atomic_<atomic_optab><mode>"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
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(unspec_volatile:ALLI
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[(atomic_op:ALLI (match_dup 0)
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(match_operand:ALLI 1 "<atomic_op_operand>" "r<const_atomic>"))
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:ALLI 3 "=&r"))
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(clobber (match_scratch:SI 4 "=&r"))]
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(define_expand "atomic_<atomic_optab><mode>"
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[(match_operand:ALLI 0 "aarch64_sync_memory_operand" "")
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(atomic_op:ALLI
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(match_operand:ALLI 1 "<atomic_op_operand>" "")
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(match_operand:SI 2 "const_int_operand"))]
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""
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{
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rtx (*gen) (rtx, rtx, rtx);
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/* Use an atomic load-operate instruction when possible. */
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if (aarch64_atomic_ldop_supported_p (<CODE>))
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gen = gen_aarch64_atomic_<atomic_optab><mode>_lse;
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else
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gen = gen_aarch64_atomic_<atomic_optab><mode>;
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emit_insn (gen (operands[0], operands[1], operands[2]));
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DONE;
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}
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)
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(define_insn_and_split "aarch64_atomic_<atomic_optab><mode>"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
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(unspec_volatile:ALLI
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[(atomic_op:ALLI (match_dup 0)
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(match_operand:ALLI 1 "<atomic_op_operand>" "r<const_atomic>"))
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(match_operand:SI 2 "const_int_operand")]
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:ALLI 3 "=&r"))
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(clobber (match_scratch:SI 4 "=&r"))]
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""
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"#"
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"&& reload_completed"
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@ -246,6 +267,25 @@
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}
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)
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(define_insn_and_split "aarch64_atomic_<atomic_optab><mode>_lse"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
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(unspec_volatile:ALLI
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[(atomic_op:ALLI (match_dup 0)
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(match_operand:ALLI 1 "<atomic_op_operand>" "r<const_atomic>"))
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(match_operand:SI 2 "const_int_operand")]
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UNSPECV_ATOMIC_OP))
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(clobber (match_scratch:ALLI 3 "=&r"))]
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"TARGET_LSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_ldop (<CODE>, operands[3], operands[0],
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operands[1], operands[2]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_nand<mode>"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
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(unspec_volatile:ALLI
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@ -268,7 +308,30 @@
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}
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)
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(define_insn_and_split "atomic_fetch_<atomic_optab><mode>"
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;; Load-operate-store, returning the updated memory data.
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(define_expand "atomic_fetch_<atomic_optab><mode>"
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[(match_operand:ALLI 0 "register_operand" "")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
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(atomic_op:ALLI
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(match_operand:ALLI 2 "<atomic_op_operand>" "")
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(match_operand:SI 3 "const_int_operand"))]
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""
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{
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rtx (*gen) (rtx, rtx, rtx, rtx);
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/* Use an atomic load-operate instruction when possible. */
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if (aarch64_atomic_ldop_supported_p (<CODE>))
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gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>_lse;
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else
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gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>;
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emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
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DONE;
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})
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(define_insn_and_split "aarch64_atomic_fetch_<atomic_optab><mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
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(set (match_dup 1)
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@ -291,6 +354,26 @@
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}
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)
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(define_insn_and_split "aarch64_atomic_fetch_<atomic_optab><mode>_lse"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(atomic_op:ALLI (match_dup 1)
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(match_operand:ALLI 2 "<atomic_op_operand>" "r<const_atomic>"))
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(match_operand:SI 3 "const_int_operand")]
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UNSPECV_ATOMIC_LDOP))]
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"TARGET_LSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_gen_atomic_ldop (<CODE>, operands[0], operands[1],
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operands[2], operands[3]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_fetch_nand<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
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@ -1,3 +1,8 @@
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/aarch64/atomic-inst-ldadd.c: New.
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* gcc.target/aarch64/atomic-inst-ldlogic.c: New.
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2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/aarch64/atomic-inst-ops.inc: (TEST_MODEL): New.
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@ -0,0 +1,58 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=armv8-a+lse" } */
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/* Test ARMv8.1-A Load-ADD instruction. */
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#include "atomic-inst-ops.inc"
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#define TEST TEST_ONE
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#define LOAD_ADD(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_fetch_add (val, foo, MODEL); \
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}
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#define LOAD_ADD_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_fetch_add (val, foo, MODEL); \
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}
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#define LOAD_SUB(FN, TY, MODEL) \
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TY FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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return __atomic_fetch_sub (val, foo, MODEL); \
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}
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#define LOAD_SUB_NORETURN(FN, TY, MODEL) \
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void FNNAME (FN, TY) (TY* val, TY* foo) \
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{ \
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__atomic_fetch_sub (val, foo, MODEL); \
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}
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TEST (load_add, LOAD_ADD)
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TEST (load_add_notreturn, LOAD_ADD_NORETURN)
|
||||
|
||||
TEST (load_sub, LOAD_SUB)
|
||||
TEST (load_sub_notreturn, LOAD_SUB_NORETURN)
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldaddb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddab\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddlb\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddalb\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldaddh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddah\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddlh\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddalh\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldadd\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldadda\t" 32} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddl\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldaddal\t" 32} } */
|
||||
|
||||
/* { dg-final { scan-assembler-not "ldaxr\t" } } */
|
||||
/* { dg-final { scan-assembler-not "stlxr\t" } } */
|
||||
/* { dg-final { scan-assembler-not "dmb" } } */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -march=armv8-a+lse" } */
|
||||
|
||||
/* Test ARMv8.1-A LD<logic-op> instruction. */
|
||||
|
||||
#include "atomic-inst-ops.inc"
|
||||
|
||||
#define TEST TEST_ONE
|
||||
|
||||
#define LOAD_OR(FN, TY, MODEL) \
|
||||
TY FNNAME (FN, TY) (TY* val, TY* foo) \
|
||||
{ \
|
||||
return __atomic_fetch_or (val, foo, MODEL); \
|
||||
}
|
||||
|
||||
#define LOAD_OR_NORETURN(FN, TY, MODEL) \
|
||||
void FNNAME (FN, TY) (TY* val, TY* foo) \
|
||||
{ \
|
||||
__atomic_fetch_or (val, foo, MODEL); \
|
||||
}
|
||||
|
||||
#define LOAD_AND(FN, TY, MODEL) \
|
||||
TY FNNAME (FN, TY) (TY* val, TY* foo) \
|
||||
{ \
|
||||
return __atomic_fetch_and (val, foo, MODEL); \
|
||||
}
|
||||
|
||||
#define LOAD_AND_NORETURN(FN, TY, MODEL) \
|
||||
void FNNAME (FN, TY) (TY* val, TY* foo) \
|
||||
{ \
|
||||
__atomic_fetch_and (val, foo, MODEL); \
|
||||
}
|
||||
|
||||
#define LOAD_XOR(FN, TY, MODEL) \
|
||||
TY FNNAME (FN, TY) (TY* val, TY* foo) \
|
||||
{ \
|
||||
return __atomic_fetch_xor (val, foo, MODEL); \
|
||||
}
|
||||
|
||||
#define LOAD_XOR_NORETURN(FN, TY, MODEL) \
|
||||
void FNNAME (FN, TY) (TY* val, TY* foo) \
|
||||
{ \
|
||||
__atomic_fetch_xor (val, foo, MODEL); \
|
||||
}
|
||||
|
||||
|
||||
TEST (load_or, LOAD_OR)
|
||||
TEST (load_or_notreturn, LOAD_OR_NORETURN)
|
||||
|
||||
TEST (load_and, LOAD_AND)
|
||||
TEST (load_and_notreturn, LOAD_AND_NORETURN)
|
||||
|
||||
TEST (load_xor, LOAD_XOR)
|
||||
TEST (load_xor_notreturn, LOAD_XOR_NORETURN)
|
||||
|
||||
/* Load-OR. */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldsetb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetab\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetlb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetalb\t" 8} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldseth\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetah\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetlh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetalh\t" 8} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldset\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldseta\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetl\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldsetal\t" 16} } */
|
||||
|
||||
/* Load-AND. */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldclrb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrab\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrlb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclralb\t" 8} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldclrh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrah\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrlh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldclralh\t" 8} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldclr\t" 8} */
|
||||
/* { dg-final { scan-assembler-times "ldclra\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldclrl\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldclral\t" 16} } */
|
||||
|
||||
/* Load-XOR. */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldeorb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorab\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorlb\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoralb\t" 8} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldeorh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorah\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorlh\t" 4} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoralh\t" 8} } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "ldeor\t" 8} */
|
||||
/* { dg-final { scan-assembler-times "ldeora\t" 16} } */
|
||||
/* { dg-final { scan-assembler-times "ldeorl\t" 8} } */
|
||||
/* { dg-final { scan-assembler-times "ldeoral\t" 16} } */
|
||||
|
||||
/* { dg-final { scan-assembler-not "ldaxr\t" } } */
|
||||
/* { dg-final { scan-assembler-not "stlxr\t" } } */
|
||||
/* { dg-final { scan-assembler-not "dmb" } } */
|
||||
Loading…
Reference in New Issue