re PR rtl-optimization/85925 (compilation of masking with 257 goes wrong in combine at -02)
PR rtl-optimization/85925 * rtl.h (word_register_operation_p): New predicate. * combine.c (record_dead_and_set_regs_1): Only apply specific handling for WORD_REGISTER_OPERATIONS targets to word_register_operation_p RTX. * rtlanal.c (nonzero_bits1): Likewise. Adjust couple of comments. (num_sign_bit_copies1): Likewise. From-SVN: r266302
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@ -130,6 +130,15 @@
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* dwarf2out.c (dwarf2out_early_global_decl): For
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decl_function_context recurse instead of calling dwarf2out_decl.
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2018-11-20 Eric Botcazou <ebotcazou@adacore.com>
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PR rtl-optimization/85925
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* rtl.h (word_register_operation_p): New predicate.
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* combine.c (record_dead_and_set_regs_1): Only apply specific handling
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for WORD_REGISTER_OPERATIONS targets to word_register_operation_p RTX.
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* rtlanal.c (nonzero_bits1): Likewise. Adjust couple of comments.
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(num_sign_bit_copies1): Likewise.
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2018-11-19 Richard Biener <rguenther@suse.de>
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PR lto/87229
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@ -13331,6 +13331,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
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&& subreg_lowpart_p (SET_DEST (setter)))
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record_value_for_reg (dest, record_dead_insn,
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WORD_REGISTER_OPERATIONS
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&& word_register_operation_p (SET_SRC (setter))
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&& paradoxical_subreg_p (SET_DEST (setter))
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? SET_SRC (setter)
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: gen_lowpart (GET_MODE (dest),
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19
gcc/rtl.h
19
gcc/rtl.h
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@ -4374,6 +4374,25 @@ strip_offset_and_add (rtx x, poly_int64_pod *offset)
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return x;
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}
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/* Return true if X is an operation that always operates on the full
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registers for WORD_REGISTER_OPERATIONS architectures. */
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inline bool
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word_register_operation_p (const_rtx x)
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{
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switch (GET_CODE (x))
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{
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case ROTATE:
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case ROTATERT:
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case SIGN_EXTRACT:
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case ZERO_EXTRACT:
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return false;
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default:
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return true;
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}
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}
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/* gtype-desc.c. */
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extern void gt_ggc_mx (rtx &);
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extern void gt_pch_nx (rtx &);
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@ -4485,12 +4485,12 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
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might be nonzero in its own mode, taking into account the fact that, on
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CISC machines, accessing an object in a wider mode generally causes the
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high-order bits to become undefined, so they are not known to be zero.
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We extend this reasoning to RISC machines for rotate operations since the
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semantics of the operations in the larger mode is not well defined. */
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We extend this reasoning to RISC machines for operations that might not
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operate on the full registers. */
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if (mode_width > xmode_width
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&& xmode_width <= BITS_PER_WORD
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&& xmode_width <= HOST_BITS_PER_WIDE_INT
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&& (!WORD_REGISTER_OPERATIONS || code == ROTATE || code == ROTATERT))
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&& !(WORD_REGISTER_OPERATIONS && word_register_operation_p (x)))
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{
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nonzero &= cached_nonzero_bits (x, xmode,
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known_x, known_mode, known_ret);
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@ -4758,13 +4758,16 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
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nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
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known_x, known_mode, known_ret);
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/* On many CISC machines, accessing an object in a wider mode
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/* On a typical CISC machine, accessing an object in a wider mode
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causes the high-order bits to become undefined. So they are
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not known to be zero. */
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not known to be zero.
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On a typical RISC machine, we only have to worry about the way
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loads are extended. Otherwise, if we get a reload for the inner
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part, it may be loaded from the stack, and then we may lose all
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the zero bits that existed before the store to the stack. */
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rtx_code extend_op;
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if ((!WORD_REGISTER_OPERATIONS
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/* If this is a typical RISC machine, we only have to worry
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about the way loads are extended. */
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|| ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
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? val_signbit_known_set_p (inner_mode, nonzero)
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: extend_op != ZERO_EXTEND)
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@ -5025,10 +5028,9 @@ num_sign_bit_copies1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
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{
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/* If this machine does not do all register operations on the entire
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register and MODE is wider than the mode of X, we can say nothing
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at all about the high-order bits. We extend this reasoning to every
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machine for rotate operations since the semantics of the operations
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in the larger mode is not well defined. */
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if (!WORD_REGISTER_OPERATIONS || code == ROTATE || code == ROTATERT)
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at all about the high-order bits. We extend this reasoning to RISC
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machines for operations that might not operate on full registers. */
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if (!(WORD_REGISTER_OPERATIONS && word_register_operation_p (x)))
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return 1;
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/* Likewise on machines that do, if the mode of the object is smaller
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/* For paradoxical SUBREGs on machines where all register operations
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affect the entire register, just look inside. Note that we are
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passing MODE to the recursive call, so the number of sign bit
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copies will remain relative to that mode, not the inner mode. */
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copies will remain relative to that mode, not the inner mode.
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/* This works only if loads sign extend. Otherwise, if we get a
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This works only if loads sign extend. Otherwise, if we get a
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reload for the inner part, it may be loaded from the stack, and
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then we lose all sign bit copies that existed before the store
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to the stack. */
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if (WORD_REGISTER_OPERATIONS
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&& load_extend_op (inner_mode) == SIGN_EXTEND
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&& paradoxical_subreg_p (x)
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@ -1,3 +1,7 @@
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2018-11-20 Eric Botcazou <ebotcazou@adacore.com>
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* gcc.c-torture/execute/20181120-1.c: New test.
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2018-11-20 Richard Biener <rguenther@suse.de>
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PR tree-optimization/88087
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@ -0,0 +1,26 @@
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/* PR rtl-optimization/85925 */
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/* Testcase by <sudi@gcc.gnu.org> */
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int a, c, d;
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volatile int b;
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int *e = &d;
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union U1 {
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unsigned f0;
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unsigned f1 : 15;
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};
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int main (void)
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{
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for (c = 0; c <= 1; c++) {
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union U1 f = {0x10101};
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if (c == 1)
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b;
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*e = f.f1;
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}
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if (d != 0x101)
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__builtin_abort ();
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return 0;
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}
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