PR target/83663 - Revert r255946
gcc/ 2018-01-08 Vidya Praveen <vidyapraveen@arm.com> PR target/83663 - Revert r255946 * config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code generation for cases where splatting a value is not useful. * simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge across a vec_duplicate and a paradoxical subreg forming a vector mode to a vec_concat. gcc/testsuite/ 2018-01-08 Vidya Praveen <vidyapraveen@arm.com> PR target/83663 - Revert r255946 * gcc.target/aarch64/vect-slp-dup.c: New. From-SVN: r256346
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Vidya Praveen
Vidya Praveen
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@ -1,3 +1,12 @@
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2018-01-08 Vidya Praveen <vidyapraveen@arm.com>
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PR target/83663 - Revert r255946
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* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code
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generation for cases where splatting a value is not useful.
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* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
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across a vec_duplicate and a paradoxical subreg forming a vector
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mode to a vec_concat.
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2018-01-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/t-aprofile (MULTILIB_MATCHES): Add mapping rules for
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@ -12129,51 +12129,9 @@ aarch64_expand_vector_init (rtx target, rtx vals)
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maxv = matches[i][1];
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}
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/* Create a duplicate of the most common element, unless all elements
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are equally useless to us, in which case just immediately set the
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vector register using the first element. */
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if (maxv == 1)
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{
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/* For vectors of two 64-bit elements, we can do even better. */
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if (n_elts == 2
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&& (inner_mode == E_DImode
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|| inner_mode == E_DFmode))
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{
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rtx x0 = XVECEXP (vals, 0, 0);
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rtx x1 = XVECEXP (vals, 0, 1);
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/* Combine can pick up this case, but handling it directly
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here leaves clearer RTL.
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This is load_pair_lanes<mode>, and also gives us a clean-up
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for store_pair_lanes<mode>. */
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if (memory_operand (x0, inner_mode)
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&& memory_operand (x1, inner_mode)
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&& !STRICT_ALIGNMENT
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&& rtx_equal_p (XEXP (x1, 0),
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plus_constant (Pmode,
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XEXP (x0, 0),
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GET_MODE_SIZE (inner_mode))))
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{
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rtx t;
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if (inner_mode == DFmode)
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t = gen_load_pair_lanesdf (target, x0, x1);
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else
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t = gen_load_pair_lanesdi (target, x0, x1);
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emit_insn (t);
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return;
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}
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}
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rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
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aarch64_emit_move (target, lowpart_subreg (mode, x, inner_mode));
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maxelement = 0;
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}
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else
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{
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rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement));
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aarch64_emit_move (target, gen_vec_duplicate (mode, x));
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}
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/* Create a duplicate of the most common element. */
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rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement));
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aarch64_emit_move (target, gen_vec_duplicate (mode, x));
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/* Insert the rest. */
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for (int i = 0; i < n_elts; i++)
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@ -5888,57 +5888,6 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
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return simplify_gen_binary (VEC_CONCAT, mode, newop0, newop1);
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}
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/* Replace:
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(vec_merge:outer (vec_duplicate:outer x:inner)
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(subreg:outer y:inner 0)
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(const_int N))
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with (vec_concat:outer x:inner y:inner) if N == 1,
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or (vec_concat:outer y:inner x:inner) if N == 2.
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We assume that degenrate cases (N == 0 or N == 3), which
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represent taking all elements from either input, are handled
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elsewhere.
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Implicitly, this means we have a paradoxical subreg, but such
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a check is cheap, so make it anyway.
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Only applies for vectors of two elements. */
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if ((GET_CODE (op0) == VEC_DUPLICATE
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|| GET_CODE (op1) == VEC_DUPLICATE)
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&& GET_MODE (op0) == GET_MODE (op1)
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&& known_eq (GET_MODE_NUNITS (GET_MODE (op0)), 2)
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&& known_eq (GET_MODE_NUNITS (GET_MODE (op1)), 2)
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&& IN_RANGE (sel, 1, 2))
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{
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rtx newop0 = op0, newop1 = op1;
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/* Canonicalize locally such that the VEC_DUPLICATE is always
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the first operand. */
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if (GET_CODE (newop1) == VEC_DUPLICATE)
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{
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std::swap (newop0, newop1);
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/* If we swap the operand order, we also need to swap
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the selector mask. */
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sel = sel == 1 ? 2 : 1;
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}
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if (GET_CODE (newop1) == SUBREG
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&& paradoxical_subreg_p (newop1)
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&& subreg_lowpart_p (newop1)
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&& GET_MODE (SUBREG_REG (newop1))
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== GET_MODE (XEXP (newop0, 0)))
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{
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newop0 = XEXP (newop0, 0);
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newop1 = SUBREG_REG (newop1);
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if (sel == 2)
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std::swap (newop0, newop1);
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return simplify_gen_binary (VEC_CONCAT, mode,
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newop0, newop1);
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}
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}
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/* Replace (vec_merge (vec_duplicate x) (vec_duplicate y)
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(const_int n))
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with (vec_concat x y) or (vec_concat y x) depending on value
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@ -1,3 +1,8 @@
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2018-01-08 Vidya Praveen <vidyapraveen@arm.com>
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PR target/83663 - Revert r255946
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* gcc.target/aarch64/vect-slp-dup.c: New.
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2018-01-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/arm/multilib.exp: Add fp16, dotprod and armv8.3-a
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@ -1,20 +0,0 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -ftree-vectorize -fno-vect-cost-model" } */
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void bar (double);
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void
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foo (double *restrict in, double *restrict in2,
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double *restrict out1, double *restrict out2)
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{
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for (int i = 0; i < 1024; i++)
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{
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out1[i] = in[i] + 2.0 * in[i+128];
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out1[i+1] = in[i+1] + 2.0 * in2[i];
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bar (in[i]);
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}
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}
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/* { dg-final { scan-assembler-not "dup\tv\[0-9\]+.2d, v\[0-9\]+" } } */
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