alpha.c (fix_operator): New.
* config/alpha/alpha.c (fix_operator): New. (divmod_operator): Tidy. (alpha_emit_xfloating_cvt): Handle UNSIGNED_FIX. * config/alpha/alpha.h (FIXUNS_TRUNC_LIKE_FIX_TRUNC): Remove. (PREDICATE_CODES): Update. * config/alpha/alpha.md (fix_truncdfsi_ieee): Use match_operator. (fix_truncdfsi_internal, fix_truncdfdi_ieee): Likewise. (fix_truncsfsi_ieee, fix_truncsfsi_internal): Likewise. (fix_truncsfdi_ieee): Likewise. (fix_truncdfdi2, fix_truncsfdi2): Turn into define_expand. (fixuns_truncdfdi2, fixuns_truncsfdi2, fixuns_trunctfdi2): New. * config/alpha/alpha-protos.h: Update. From-SVN: r72677
This commit is contained in:
parent
91999e1db8
commit
64bb2e1dd4
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@ -1,3 +1,18 @@
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2003-10-19 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.c (fix_operator): New.
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(divmod_operator): Tidy.
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(alpha_emit_xfloating_cvt): Handle UNSIGNED_FIX.
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* config/alpha/alpha.h (FIXUNS_TRUNC_LIKE_FIX_TRUNC): Remove.
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(PREDICATE_CODES): Update.
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* config/alpha/alpha.md (fix_truncdfsi_ieee): Use match_operator.
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(fix_truncdfsi_internal, fix_truncdfdi_ieee): Likewise.
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(fix_truncsfsi_ieee, fix_truncsfsi_internal): Likewise.
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(fix_truncsfdi_ieee): Likewise.
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(fix_truncdfdi2, fix_truncsfdi2): Turn into define_expand.
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(fixuns_truncdfdi2, fixuns_truncsfdi2, fixuns_trunctfdi2): New.
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* config/alpha/alpha-protos.h: Update.
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2003-10-19 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.h (INITIALIZE_TRAMPOLINE): Simplify.
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@ -75,6 +75,7 @@ extern int alpha_swapped_comparison_operator (rtx, enum machine_mode);
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extern int signed_comparison_operator (rtx, enum machine_mode);
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extern int alpha_fp_comparison_operator (rtx, enum machine_mode);
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extern int divmod_operator (rtx, enum machine_mode);
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extern int fix_operator (rtx, enum machine_mode);
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extern int aligned_memory_operand (rtx, enum machine_mode);
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extern int unaligned_memory_operand (rtx, enum machine_mode);
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extern int reg_or_unaligned_mem_operand (rtx, enum machine_mode);
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@ -1179,16 +1179,19 @@ alpha_fp_comparison_operator (rtx op, enum machine_mode mode)
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int
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divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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switch (GET_CODE (op))
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{
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case DIV: case MOD: case UDIV: case UMOD:
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return 1;
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enum rtx_code code = GET_CODE (op);
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default:
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break;
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}
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return (code == DIV || code == MOD || code == UDIV || code == UMOD);
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}
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return 0;
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/* Return 1 if this is a float->int conversion operator. */
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int
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fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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enum rtx_code code = GET_CODE (op);
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return (code == FIX || code == UNSIGNED_FIX);
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}
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/* Return 1 if this memory address is a known aligned register plus
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@ -3774,11 +3777,15 @@ alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
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/* Emit an X_floating library function call for a conversion. */
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void
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alpha_emit_xfloating_cvt (enum rtx_code code, rtx operands[])
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alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
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{
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int noperands = 1, mode;
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rtx out_operands[2];
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const char *func;
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enum rtx_code code = orig_code;
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if (code == UNSIGNED_FIX)
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code = FIX;
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func = alpha_lookup_xfloating_lib_func (code);
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@ -3801,7 +3808,8 @@ alpha_emit_xfloating_cvt (enum rtx_code code, rtx operands[])
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}
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alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
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gen_rtx_fmt_e (code, GET_MODE (operands[0]),
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gen_rtx_fmt_e (orig_code,
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GET_MODE (operands[0]),
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operands[1]));
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}
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@ -1338,14 +1338,6 @@ do { \
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/* Define this as 1 if `char' should by default be signed; else as 0. */
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#define DEFAULT_SIGNED_CHAR 1
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/* This flag, if defined, says the same insns that convert to a signed fixnum
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also convert validly to an unsigned one.
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We actually lie a bit here as overflow conditions are different. But
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they aren't being checked anyway. */
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#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
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/* Max number of bytes we can move to or from memory
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in one reasonably fast instruction. */
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@ -1654,6 +1646,7 @@ do { \
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{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
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{"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
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{"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
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{"fix_operator", {FIX, UNSIGNED_FIX}}, \
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{"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \
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{"samegp_function_operand", {SYMBOL_REF}}, \
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{"direct_call_operand", {SYMBOL_REF}}, \
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@ -2337,13 +2337,15 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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(define_insn_and_split "*fix_truncdfsi_ieee"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
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(subreg:SI
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(match_operator:DI 4 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
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(clobber (match_scratch:DI 2 "=&f"))
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(clobber (match_scratch:SI 3 "=&f"))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (fix:DI (match_dup 1)))
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[(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
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(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 3))]
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""
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@ -2352,22 +2354,25 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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(define_insn_and_split "*fix_truncdfsi_internal"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
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(subreg:SI
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(match_operator:DI 3 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
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(clobber (match_scratch:DI 2 "=f"))]
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"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (fix:DI (match_dup 1)))
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(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 3))]
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[(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
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(set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 4))]
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;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
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"operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
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"operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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(define_insn "*fix_truncdfdi_ieee"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
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(fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
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(match_operator:DI 2 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"cvt%-q%/ %R1,%0"
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[(set_attr "type" "fadd")
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@ -2375,9 +2380,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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(set_attr "round_suffix" "c")
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(set_attr "trap_suffix" "v_sv_svi")])
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(define_insn "fix_truncdfdi2"
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(define_insn "*fix_truncdfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
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(fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
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(match_operator:DI 2 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
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"TARGET_FP"
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"cvt%-q%/ %R1,%0"
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[(set_attr "type" "fadd")
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(set_attr "round_suffix" "c")
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(set_attr "trap_suffix" "v_sv_svi")])
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(define_expand "fix_truncdfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
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(fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
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"TARGET_FP"
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"")
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(define_expand "fixuns_truncdfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
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(unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
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"TARGET_FP"
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"")
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;; Likewise between SFmode and SImode.
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(define_insn_and_split "*fix_truncsfsi_ieee"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(subreg:SI (fix:DI (float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
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(subreg:SI
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(match_operator:DI 4 "fix_operator"
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[(float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
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(clobber (match_scratch:DI 2 "=&f"))
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(clobber (match_scratch:SI 3 "=&f"))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
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[(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
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(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 3))]
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""
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@ -2405,24 +2425,26 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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(define_insn_and_split "*fix_truncsfsi_internal"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(subreg:SI (fix:DI (float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
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(subreg:SI
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(match_operator:DI 3 "fix_operator"
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[(float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
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(clobber (match_scratch:DI 2 "=f"))]
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"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
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(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 3))]
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[(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
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(set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 4))]
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;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
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"operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
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"operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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(define_insn "*fix_truncsfdi_ieee"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
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(fix:DI (float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))))]
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(match_operator:DI 2 "fix_operator"
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[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"cvt%-q%/ %R1,%0"
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[(set_attr "type" "fadd")
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@ -2430,10 +2452,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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(set_attr "round_suffix" "c")
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(set_attr "trap_suffix" "v_sv_svi")])
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(define_insn "fix_truncsfdi2"
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(define_insn "*fix_truncsfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
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(fix:DI (float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))))]
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(match_operator:DI 2 "fix_operator"
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[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
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"TARGET_FP"
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"cvt%-q%/ %R1,%0"
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[(set_attr "type" "fadd")
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@ -2441,12 +2463,31 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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(set_attr "round_suffix" "c")
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(set_attr "trap_suffix" "v_sv_svi")])
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(define_expand "fix_truncsfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
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(fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
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"TARGET_FP"
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"")
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(define_expand "fixuns_truncsfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
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(unsigned_fix:DI
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(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
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"TARGET_FP"
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"")
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(define_expand "fix_trunctfdi2"
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[(use (match_operand:DI 0 "register_operand" ""))
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(use (match_operand:TF 1 "general_operand" ""))]
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"TARGET_HAS_XFLOATING_LIBS"
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"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
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(define_expand "fixuns_trunctfdi2"
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[(use (match_operand:DI 0 "register_operand" ""))
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(use (match_operand:TF 1 "general_operand" ""))]
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"TARGET_HAS_XFLOATING_LIBS"
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"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
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(define_insn "*floatdisf_ieee"
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[(set (match_operand:SF 0 "register_operand" "=&f")
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(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
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