From 64e7e238113b86518981df0c7f24c60616f59511 Mon Sep 17 00:00:00 2001 From: Sandra Loosemore Date: Sat, 28 Apr 2007 13:47:28 -0400 Subject: [PATCH] mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16. 2007-04-28 Sandra Loosemore Nigel Stephens gcc/ * config/mips/mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16. Co-Authored-By: Nigel Stephens From-SVN: r124261 --- gcc/ChangeLog | 5 +++++ gcc/config/mips/mips.h | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 682195135c5..c6282e0a9eb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2007-04-28 Sandra Loosemore + Nigel Stephens + + * config/mips/mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16. + 2007-04-28 Jan Hubicka * config/alpha/alpha.c (alpha_output_mi_thunk_osf): Use diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 72845436cfd..e3c631e087e 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2240,8 +2240,11 @@ typedef struct mips_args { difference in cost between byte and (aligned) word loads. On RISC machines, it tends to generate better code to define - this as 1, since it avoids making a QI or HI mode register. */ -#define SLOW_BYTE_ACCESS 1 + this as 1, since it avoids making a QI or HI mode register. + + But, generating word accesses for -mips16 is generally bad as shifts + (often extended) would be needed for byte accesses. */ +#define SLOW_BYTE_ACCESS (!TARGET_MIPS16) /* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */