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@ -1,3 +1,273 @@
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2021-03-26 David Edelsohn <dje.gcc@gmail.com>
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* config/rs6000/aix.h (ADJUST_FIELD_ALIGN): Call function.
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* config/rs6000/rs6000-protos.h (rs6000_special_adjust_field_align):
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Declare.
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* config/rs6000/rs6000.c (rs6000_special_adjust_field_align): New.
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(rs6000_special_round_type_align): Recursively check innermost first
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field.
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2021-03-26 Jakub Jelinek <jakub@redhat.com>
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PR debug/99334
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* dwarf2out.h (struct dw_fde_node): Add rule18 member.
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* dwarf2cfi.c (dwarf2out_frame_debug_expr): When handling (set hfp sp)
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assignment with drap_reg active, queue reg save for hfp with offset 0
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and flush queued reg saves. When handling a push with rule18,
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defer queueing reg save for hfp and just assert the offset is 0.
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(scan_trace): Assert that fde->rule18 is false.
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2021-03-26 Vladimir Makarov <vmakarov@redhat.com>
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PR target/99766
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* ira-costs.c (record_reg_classes): Put case with
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CT_RELAXED_MEMORY adjacent to one with CT_MEMORY.
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* ira.c (ira_setup_alts): Ditto.
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* lra-constraints.c (process_alt_operands): Ditto.
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* recog.c (asm_operand_ok): Ditto.
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* reload.c (find_reloads): Ditto.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h
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(cpu_addrcost_table::post_modify_ld3_st3): New member variable.
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(cpu_addrcost_table::post_modify_ld4_st4): Likewise.
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* config/aarch64/aarch64.c (generic_addrcost_table): Update
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accordingly, using the same costs as for post_modify.
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(exynosm1_addrcost_table, xgene1_addrcost_table): Likewise.
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(thunderx2t99_addrcost_table, thunderx3t110_addrcost_table):
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(tsv110_addrcost_table, qdf24xx_addrcost_table): Likewise.
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(a64fx_addrcost_table): Likewise.
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(neoversev1_addrcost_table): New.
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(neoversev1_tunings): Use neoversev1_addrcost_table.
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(aarch64_address_cost): Use the new post_modify costs for CImode
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and XImode.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.opt
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(-param=aarch64-loop-vect-issue-rate-niters=): New parameter.
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* doc/invoke.texi: Document it.
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* config/aarch64/aarch64-protos.h (aarch64_base_vec_issue_info)
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(aarch64_scalar_vec_issue_info, aarch64_simd_vec_issue_info)
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(aarch64_advsimd_vec_issue_info, aarch64_sve_vec_issue_info)
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(aarch64_vec_issue_info): New structures.
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(cpu_vector_cost): Write comments above the variables rather
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than to the side.
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(cpu_vector_cost::issue_info): New member variable.
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* config/aarch64/aarch64.c: Include gimple-pretty-print.h
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and tree-ssa-loop-niter.h.
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(generic_vector_cost, a64fx_vector_cost, qdf24xx_vector_cost)
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(thunderx_vector_cost, tsv110_vector_cost, cortexa57_vector_cost)
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(exynosm1_vector_cost, xgene1_vector_cost, thunderx2t99_vector_cost)
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(thunderx3t110_vector_cost): Initialize issue_info to null.
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(neoversev1_scalar_issue_info, neoversev1_advsimd_issue_info)
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(neoversev1_sve_issue_info, neoversev1_vec_issue_info): New structures.
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(neoversev1_vector_cost): Use them.
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(aarch64_vec_op_count, aarch64_sve_op_count): New structures.
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(aarch64_vector_costs::saw_sve_only_op): New member variable.
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(aarch64_vector_costs::num_vector_iterations): Likewise.
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(aarch64_vector_costs::scalar_ops): Likewise.
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(aarch64_vector_costs::advsimd_ops): Likewise.
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(aarch64_vector_costs::sve_ops): Likewise.
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(aarch64_vector_costs::seen_loads): Likewise.
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(aarch64_simd_vec_costs_for_flags): New function.
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(aarch64_analyze_loop_vinfo): Initialize num_vector_iterations.
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Count the number of predicate operations required by SVE WHILE
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instructions.
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(aarch64_comparison_type, aarch64_multiply_add_p): New functions.
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(aarch64_sve_only_stmt_p, aarch64_in_loop_reduction_latency): Likewise.
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(aarch64_count_ops): Likewise.
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(aarch64_add_stmt_cost): Record whether see an SVE operation
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that cannot currently be implementing using Advanced SIMD.
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Record issue information about the scalar, Advanced SIMD
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and (where relevant) SVE versions of a loop.
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(aarch64_vec_op_count::dump): New function.
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(aarch64_sve_op_count::dump): Likewise.
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(aarch64_estimate_min_cycles_per_iter): Likewise.
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(aarch64_adjust_body_cost): If issue information is available,
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try to compare the issue rates of the various loop implementations
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and increase or decrease the vector body cost accordingly.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.c (aarch64_detect_vector_stmt_subtype):
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Assume a zero cost for induction phis.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.c (aarch64_embedded_comparison_type): New
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function.
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(aarch64_adjust_stmt_cost): Add the costs of embedded scalar and
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vector comparisons.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.c (aarch64_detect_scalar_stmt_subtype):
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New function.
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(aarch64_add_stmt_cost): Call it.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-tuning-flags.def (matched_vector_throughput):
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New tuning parameter.
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* config/aarch64/aarch64.c (neoversev1_tunings): Use it.
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(aarch64_estimated_sve_vq): New function.
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(aarch64_vector_costs::analyzed_vinfo): New member variable.
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(aarch64_vector_costs::is_loop): Likewise.
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(aarch64_vector_costs::unrolled_advsimd_niters): Likewise.
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(aarch64_vector_costs::unrolled_advsimd_stmts): Likewise.
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(aarch64_record_potential_advsimd_unrolling): New function.
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(aarch64_analyze_loop_vinfo, aarch64_analyze_bb_vinfo): Likewise.
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(aarch64_add_stmt_cost): Call aarch64_analyze_loop_vinfo or
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aarch64_analyze_bb_vinfo on the first use of a costs structure.
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Detect whether we're vectorizing a loop for SVE that might be
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completely unrolled if it used Advanced SIMD instead.
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(aarch64_adjust_body_cost_for_latency): New function.
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(aarch64_finish_cost): Call it.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.c (aarch64_vector_costs): New structure.
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(aarch64_init_cost): New function.
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(aarch64_add_stmt_cost): Use aarch64_vector_costs instead of
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the default unsigned[3].
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(aarch64_finish_cost, aarch64_destroy_cost_data): New functions.
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(TARGET_VECTORIZE_INIT_COST): Override.
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(TARGET_VECTORIZE_FINISH_COST): Likewise.
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(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.c (neoversev1_advsimd_vector_cost)
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(neoversev1_sve_vector_cost): New cost structures.
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(neoversev1_vector_cost): Likewise.
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(neoversev1_tunings): Use them. Enable use_new_vector_costs.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h
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(sve_vec_cost::scatter_store_elt_cost): New member variable.
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* config/aarch64/aarch64.c (generic_sve_vector_cost): Update
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accordingly, taking the cost from the cost of a scalar_store.
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(a64fx_sve_vector_cost): Likewise.
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(aarch64_detect_vector_stmt_subtype): Detect scatter stores.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h
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(simd_vec_cost::store_elt_extra_cost): New member variable.
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* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
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accordingly, using the vec_to_scalar cost for the new field.
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(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
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(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
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(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
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(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
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(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
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(thunderx3t110_advsimd_vector_cost): Likewise.
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(aarch64_detect_vector_stmt_subtype): Detect single-element stores.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h (simd_vec_cost::ld2_st2_permute_cost)
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(simd_vec_cost::ld3_st3_permute_cost): New member variables.
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(simd_vec_cost::ld4_st4_permute_cost): Likewise.
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* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
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accordingly, using zero for the new costs.
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(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
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(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
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(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
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(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
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(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
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(thunderx3t110_advsimd_vector_cost): Likewise.
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(aarch64_ld234_st234_vectors): New function.
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(aarch64_adjust_stmt_cost): Likewise.
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(aarch64_add_stmt_cost): Call aarch64_adjust_stmt_cost if using
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the new vector costs.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h (sve_vec_cost): Turn into a
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derived class of simd_vec_cost. Add information about CLAST[AB]
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and FADDA instructions.
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* config/aarch64/aarch64.c (generic_sve_vector_cost): Update
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accordingly, using the vec_to_scalar costs for the new fields.
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(a64fx_sve_vector_cost): Likewise.
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(aarch64_reduc_type): New function.
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(aarch64_sve_in_loop_reduction_latency): Likewise.
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(aarch64_detect_vector_stmt_subtype): Take a vinfo parameter.
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Use aarch64_sve_in_loop_reduction_latency to handle SVE reductions
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that occur in the loop body.
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(aarch64_add_stmt_cost): Update call accordingly.
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2021-03-26 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-tuning-flags.def (use_new_vector_costs):
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New tuning flag.
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* config/aarch64/aarch64-protos.h (simd_vec_cost): Put comments
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above the fields rather than to the right.
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(simd_vec_cost::reduc_i8_cost): New member variable.
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(simd_vec_cost::reduc_i16_cost): Likewise.
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(simd_vec_cost::reduc_i32_cost): Likewise.
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(simd_vec_cost::reduc_i64_cost): Likewise.
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(simd_vec_cost::reduc_f16_cost): Likewise.
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(simd_vec_cost::reduc_f32_cost): Likewise.
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(simd_vec_cost::reduc_f64_cost): Likewise.
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* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
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accordingly, using the vec_to_scalar_cost for the new fields.
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(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
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(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
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(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
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(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
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(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
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(thunderx3t110_advsimd_vector_cost): Likewise.
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(aarch64_use_new_vector_costs_p): New function.
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(aarch64_simd_vec_costs): New function, split out from...
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(aarch64_builtin_vectorization_cost): ...here.
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(aarch64_is_reduction): New function.
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(aarch64_detect_vector_stmt_subtype): Likewise.
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(aarch64_add_stmt_cost): Call aarch64_detect_vector_stmt_subtype if
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using the new vector costs.
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2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
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PR ipa/99466
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* tree-emutls.c (get_emutls_init_templ_addr): Mark initializer of weak
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TLS declarations as public.
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2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
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* config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define.
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* config/arm/arm-d.c (IN_TARGET_CODE): Likewise.
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* config/i386/i386-d.c (IN_TARGET_CODE): Likewise.
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* config/mips/mips-d.c (IN_TARGET_CODE): Likewise.
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* config/pa/pa-d.c (IN_TARGET_CODE): Likewise.
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* config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise.
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* config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise.
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* config/s390/s390-d.c (IN_TARGET_CODE): Likewise.
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* config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise.
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2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
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PR d/91595
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* config.gcc (*-*-cygwin*): Add winnt-d.o
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(*-*-mingw*): Likewise.
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* config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): New macro.
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* config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Likewise.
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* config/i386/t-cygming: Add winnt-d.o.
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* config/i386/winnt-d.c: New file.
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2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
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* config/freebsd-d.c: Include memmodel.h.
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2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org>
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PR d/99691
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* config.gcc (*-*-openbsd*): Add openbsd-d.o.
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* config/t-openbsd: Add openbsd-d.o.
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* config/openbsd-d.c: New file.
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2021-03-25 Stam Markianos-Wright <stam.markianos-wright@arm.com>
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PR tree-optimization/96974
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