MAINTAINERS: Add myself as a maintainer for the RX port.
* MAINTAINERS: Add myself as a maintainer for the RX port.
gcc
* config.gcc: Add support for RX target.
* config/rx: New directory.
* config/rx/constraints.md: New file.
* config/rx/predicates.md: New file.
* config/rx/rx.c: New file.
* config/rx/rx.h: New file.
* config/rx/rx.md: New file.
* config/rx/rx.opt: New file.
* config/rx/rx-protos.h: New file.
* config/rx/t-rx: New file.
* doc/extend.texi: Document RX function attributes.
* doc/invoke.texi: Document RX specific command line options.
* doc/contrib.texi: Document RX contribution.
* doc/md.texi: Document RX constraints.
* doc/install.texi: Document RX support.
libgcc
* config.host: Add support for RX target.
* config/rx: New directory.
* config/rx/rx-abi-functions.c: New file. Supplementary
functions for libgcc to support the RX ABI.
* config/rx/rx-abi.h: New file. Supplementary header file for
libgcc RX ABI functions.
* config/rx/t-rx: New file: Makefile fragment for building
libgcc for the RX.
gcc/testsuite
* lib/target-supports.exp (check_profiling_available):
Profiling is not, currently, available for the RX port.
(check_effective_target_hard_float): Add support for RX
target.
* gcc.target/rx: New directory.
* gcc.target/rx/builtins.c: New test file.
* gcc.target/rx/interrupts.c: New test file.
* gcc.target/rx/rx-abi-function-tests.c: New test file.
* gcc.target/rx/zero-width-bitfield.c: New test file.
* gcc.target/rx/i272091.c: New test file.
* gcc.target/rx/packed-struct.c: New test file.
* gcc.target/rx/rx.exp: New file: Drives RX tests.
From-SVN: r153557
This commit is contained in:
Nick Clifton
Nick Clifton
parent
03428d41b1
commit
65a324b459
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@ -1,3 +1,7 @@
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|||
2009-10-16 Nick Clifton <nickc@redhat.com>
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* MAINTAINERS: Add myself as a maintainer for the RX port.
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2009-10-26 Johannes Singler <singler@kit.edu>
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* MAINTAINERS (Write After Approval): Update my e-mail address.
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|
|
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@ -82,6 +82,7 @@ picochip port Daniel Towner dant@picochip.com
|
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rs6000 port Geoff Keating geoffk@geoffk.org
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rs6000 port David Edelsohn edelsohn@gnu.org
|
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rs6000 vector extns Aldy Hernandez aldyh@redhat.com
|
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rx port Nick Clifton nickc@redhat.com
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s390 port Hartmut Penner hpenner@de.ibm.com
|
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s390 port Ulrich Weigand uweigand@de.ibm.com
|
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s390 port Andreas Krebbel Andreas.Krebbel@de.ibm.com
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|
|
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@ -1,3 +1,21 @@
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2009-10-26 Nick Clifton <nickc@redhat.com>
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* config.gcc: Add support for RX target.
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* config/rx: New directory.
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* config/rx/constraints.md: New file.
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* config/rx/predicates.md: New file.
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* config/rx/rx.c: New file.
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* config/rx/rx.h: New file.
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* config/rx/rx.md: New file.
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* config/rx/rx.opt: New file.
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* config/rx/rx-protos.h: New file.
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* config/rx/t-rx: New file.
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* doc/extend.texi: Document RX function attributes.
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* doc/invoke.texi: Document RX specific command line options.
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* doc/contrib.texi: Document RX contribution.
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* doc/md.texi: Document RX constraints.
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* doc/install.texi: Document RX support.
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2009-10-26 Michael Matz <matz@suse.de>
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PR tree-optimization/41783
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|
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@ -287,7 +287,7 @@ i[34567]86-*-*)
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extra_headers="cpuid.h mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
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pmmintrin.h tmmintrin.h ammintrin.h smmintrin.h
|
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nmmintrin.h bmmintrin.h fma4intrin.h wmmintrin.h
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immintrin.h x86intrin.h avxintrin.h
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||||
immintrin.h x86intrin.h avxintrin.h
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ia32intrin.h cross-stdarg.h"
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;;
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x86_64-*-*)
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||||
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|
@ -2077,6 +2077,10 @@ rs6000-ibm-aix[6789].* | powerpc-ibm-aix[6789].*)
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use_gcc_stdint=wrap
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extra_headers=altivec.h
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;;
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rx-*-elf*)
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tm_file="dbxelf.h elfos.h svr4.h newlib-stdint.h ${tm_file} ../../libgcc/config/rx/rx-abi.h"
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tmake_file="${tmake_file} rx/t-rx"
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;;
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s390-*-linux*)
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tm_file="s390/s390.h dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h s390/linux.h"
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;;
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|
|
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|
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@ -0,0 +1,81 @@
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;; Constraint definitions for Renesas RX.
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;; Contributed by Red Hat.
|
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;;
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;; This file is part of GCC.
|
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;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
|
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(define_constraint "Symbol"
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"@internal Constraint on the type of rtx allowed in call insns"
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(match_test "GET_CODE (op) == SYMBOL_REF")
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)
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|
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(define_constraint "Int08"
|
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"@internal A signed or unsigned 8-bit immediate value"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, (-1 << 8), (1 << 8) - 1)")
|
||||
)
|
||||
)
|
||||
|
||||
(define_constraint "Sint08"
|
||||
"@internal A signed 8-bit immediate value"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, (-1 << 7), (1 << 7) - 1)")
|
||||
)
|
||||
)
|
||||
|
||||
(define_constraint "Sint16"
|
||||
"@internal A signed 16-bit immediate value"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, (-1 << 15), (1 << 15) - 1)")
|
||||
)
|
||||
)
|
||||
|
||||
(define_constraint "Sint24"
|
||||
"@internal A signed 24-bit immediate value"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, (-1 << 23), (1 << 23) - 1)")
|
||||
)
|
||||
)
|
||||
|
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;; This constraint is used by the SUBSI3 pattern because the
|
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;; RX SUB instruction can only take a 4-bit unsigned integer
|
||||
;; value.
|
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(define_constraint "Uint04"
|
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"@internal An unsigned 4-bit immediate value"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, 0, 15)")
|
||||
)
|
||||
)
|
||||
|
||||
;; This is used in arithmetic and logic instructions for
|
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;; a source operand that lies in memory and which satisfies
|
||||
;; rx_restricted_memory_address().
|
||||
|
||||
(define_memory_constraint "Q"
|
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"A MEM which only uses REG or REG+INT addressing."
|
||||
(and (match_code "mem")
|
||||
(ior (match_code "reg" "0")
|
||||
(and (match_code "plus" "0")
|
||||
(and (match_code "reg,subreg" "00")
|
||||
(match_code "const_int" "01")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,282 @@
|
|||
;; Predicate definitions for Renesas RX.
|
||||
;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
|
||||
;; Contributed by Red Hat.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
|
||||
|
||||
;; Check that the operand is suitable for a call insn.
|
||||
;; Only registers and symbol refs are allowed.
|
||||
|
||||
(define_predicate "rx_call_operand"
|
||||
(match_code "symbol_ref,reg")
|
||||
)
|
||||
|
||||
;; For sibcall operations we can only use a symbolic address.
|
||||
|
||||
(define_predicate "rx_symbolic_call_operand"
|
||||
(match_code "symbol_ref")
|
||||
)
|
||||
|
||||
;; Check that the operand is suitable for a shift insn
|
||||
;; Only small integers or a value in a register are permitted.
|
||||
|
||||
(define_predicate "rx_shift_operand"
|
||||
(match_code "const_int,reg")
|
||||
{
|
||||
if (CONST_INT_P (op))
|
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return IN_RANGE (INTVAL (op), 0, 31);
|
||||
return true;
|
||||
}
|
||||
)
|
||||
|
||||
;; Check that the operand is suitable as the source operand
|
||||
;; for a logic or arithmeitc instruction. Registers, integers
|
||||
;; and a restricted subset of memory addresses are allowed.
|
||||
|
||||
(define_predicate "rx_source_operand"
|
||||
(match_code "const_int,reg,mem")
|
||||
{
|
||||
if (CONST_INT_P (op))
|
||||
return rx_is_legitimate_constant (op);
|
||||
|
||||
if (! MEM_P (op))
|
||||
return true;
|
||||
|
||||
/* Do not allow size conversions whilst accessing memory. */
|
||||
if (GET_MODE (op) != mode)
|
||||
return false;
|
||||
|
||||
return rx_is_restricted_memory_address (XEXP (op, 0), mode);
|
||||
}
|
||||
)
|
||||
|
||||
;; Check that the operand is suitable as the source operand
|
||||
;; for a comparison instruction. This is the same as
|
||||
;; rx_source_operand except that SUBREGs are allowed but
|
||||
;; CONST_INTs are not.
|
||||
|
||||
(define_predicate "rx_compare_operand"
|
||||
(match_code "subreg,reg,mem")
|
||||
{
|
||||
if (GET_CODE (op) == SUBREG)
|
||||
return REG_P (XEXP (op, 0));
|
||||
|
||||
if (! MEM_P (op))
|
||||
return true;
|
||||
|
||||
return rx_is_restricted_memory_address (XEXP (op, 0), mode);
|
||||
}
|
||||
)
|
||||
|
||||
;; Return true if OP is a store multiple operation. This looks like:
|
||||
;;
|
||||
;; [(set (SP) (MINUS (SP) (INT)))
|
||||
;; (set (MEM (SP)) (REG))
|
||||
;; (set (MEM (MINUS (SP) (INT))) (REG)) {optionally repeated}
|
||||
;; ]
|
||||
|
||||
(define_special_predicate "rx_store_multiple_vector"
|
||||
(match_code "parallel")
|
||||
{
|
||||
int count = XVECLEN (op, 0);
|
||||
unsigned int src_regno;
|
||||
rtx element;
|
||||
int i;
|
||||
|
||||
/* Perform a quick check so we don't blow up below. */
|
||||
if (count <= 2)
|
||||
return false;
|
||||
|
||||
/* Check that the first element of the vector is the stack adjust. */
|
||||
element = XVECEXP (op, 0, 0);
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| REGNO (SET_DEST (element)) != SP_REG
|
||||
|| GET_CODE (SET_SRC (element)) != MINUS
|
||||
|| ! REG_P (XEXP (SET_SRC (element), 0))
|
||||
|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
|
||||
|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
|
||||
return false;
|
||||
|
||||
/* Check that the next element is the first push. */
|
||||
element = XVECEXP (op, 0, 1);
|
||||
if ( ! SET_P (element)
|
||||
|| ! MEM_P (SET_DEST (element))
|
||||
|| ! REG_P (XEXP (SET_DEST (element), 0))
|
||||
|| REGNO (XEXP (SET_DEST (element), 0)) != SP_REG
|
||||
|| ! REG_P (SET_SRC (element)))
|
||||
return false;
|
||||
|
||||
src_regno = REGNO (SET_SRC (element));
|
||||
|
||||
/* Check that the remaining elements use SP-<disp>
|
||||
addressing and incremental register numbers. */
|
||||
for (i = 2; i < count; i++)
|
||||
{
|
||||
element = XVECEXP (op, 0, i);
|
||||
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_SRC (element))
|
||||
|| GET_MODE (SET_SRC (element)) != SImode
|
||||
|| REGNO (SET_SRC (element)) != src_regno + (i - 1)
|
||||
|| ! MEM_P (SET_DEST (element))
|
||||
|| GET_MODE (SET_DEST (element)) != SImode
|
||||
|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
|
||||
|| ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
|
||||
|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
|
||||
|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
|
||||
|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
|
||||
!= (i - 1) * GET_MODE_SIZE (SImode))
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
})
|
||||
|
||||
;; Return true if OP is a load multiple operation.
|
||||
;; This looks like:
|
||||
;; [(set (SP) (PLUS (SP) (INT)))
|
||||
;; (set (REG) (MEM (SP)))
|
||||
;; (set (REG) (MEM (PLUS (SP) (INT)))) {optionally repeated}
|
||||
;; ]
|
||||
|
||||
(define_special_predicate "rx_load_multiple_vector"
|
||||
(match_code "parallel")
|
||||
{
|
||||
int count = XVECLEN (op, 0);
|
||||
unsigned int dest_regno;
|
||||
rtx element;
|
||||
int i;
|
||||
|
||||
/* Perform a quick check so we don't blow up below. */
|
||||
if (count <= 2)
|
||||
return false;
|
||||
|
||||
/* Check that the first element of the vector is the stack adjust. */
|
||||
element = XVECEXP (op, 0, 0);
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| REGNO (SET_DEST (element)) != SP_REG
|
||||
|| GET_CODE (SET_SRC (element)) != PLUS
|
||||
|| ! REG_P (XEXP (SET_SRC (element), 0))
|
||||
|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
|
||||
|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
|
||||
return false;
|
||||
|
||||
/* Check that the next element is the first push. */
|
||||
element = XVECEXP (op, 0, 1);
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| ! MEM_P (SET_SRC (element))
|
||||
|| ! REG_P (XEXP (SET_SRC (element), 0))
|
||||
|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
|
||||
return false;
|
||||
|
||||
dest_regno = REGNO (SET_DEST (element));
|
||||
|
||||
/* Check that the remaining elements use SP+<disp>
|
||||
addressing and incremental register numbers. */
|
||||
for (i = 2; i < count; i++)
|
||||
{
|
||||
element = XVECEXP (op, 0, i);
|
||||
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| GET_MODE (SET_DEST (element)) != SImode
|
||||
|| REGNO (SET_DEST (element)) != dest_regno + (i - 1)
|
||||
|| ! MEM_P (SET_SRC (element))
|
||||
|| GET_MODE (SET_SRC (element)) != SImode
|
||||
|| GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
|
||||
|| ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
|
||||
|| REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
|
||||
|| ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
|
||||
|| INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
|
||||
!= (i - 1) * GET_MODE_SIZE (SImode))
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
})
|
||||
|
||||
;; Return true if OP is a pop-and-return load multiple operation.
|
||||
;; This looks like:
|
||||
;; [(set (SP) (PLUS (SP) (INT)))
|
||||
;; (set (REG) (MEM (SP)))
|
||||
;; (set (REG) (MEM (PLUS (SP) (INT)))) {optional and possibly repeated}
|
||||
;; (return)
|
||||
;; ]
|
||||
|
||||
(define_special_predicate "rx_rtsd_vector"
|
||||
(match_code "parallel")
|
||||
{
|
||||
int count = XVECLEN (op, 0);
|
||||
unsigned int dest_regno;
|
||||
rtx element;
|
||||
int i;
|
||||
|
||||
/* Perform a quick check so we don't blow up below. */
|
||||
if (count <= 2)
|
||||
return false;
|
||||
|
||||
/* Check that the first element of the vector is the stack adjust. */
|
||||
element = XVECEXP (op, 0, 0);
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| REGNO (SET_DEST (element)) != SP_REG
|
||||
|| GET_CODE (SET_SRC (element)) != PLUS
|
||||
|| ! REG_P (XEXP (SET_SRC (element), 0))
|
||||
|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
|
||||
|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
|
||||
return false;
|
||||
|
||||
/* Check that the next element is the first push. */
|
||||
element = XVECEXP (op, 0, 1);
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| ! MEM_P (SET_SRC (element))
|
||||
|| ! REG_P (XEXP (SET_SRC (element), 0))
|
||||
|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
|
||||
return false;
|
||||
|
||||
dest_regno = REGNO (SET_DEST (element));
|
||||
|
||||
/* Check that the remaining elements, if any, and except
|
||||
for the last one, use SP+<disp> addressing and incremental
|
||||
register numbers. */
|
||||
for (i = 2; i < count - 1; i++)
|
||||
{
|
||||
element = XVECEXP (op, 0, i);
|
||||
|
||||
if ( ! SET_P (element)
|
||||
|| ! REG_P (SET_DEST (element))
|
||||
|| GET_MODE (SET_DEST (element)) != SImode
|
||||
|| REGNO (SET_DEST (element)) != dest_regno + (i - 1)
|
||||
|| ! MEM_P (SET_SRC (element))
|
||||
|| GET_MODE (SET_SRC (element)) != SImode
|
||||
|| GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
|
||||
|| ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
|
||||
|| REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
|
||||
|| ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
|
||||
|| INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
|
||||
!= (i - 1) * GET_MODE_SIZE (SImode))
|
||||
return false;
|
||||
}
|
||||
|
||||
/* The last element must be a RETURN. */
|
||||
element = XVECEXP (op, 0, count - 1);
|
||||
return GET_CODE (element) == RETURN;
|
||||
})
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/* Exported function prototypes from the Renesas RX backend.
|
||||
Copyright (C) 2008, 2009 Free Software Foundation, Inc.
|
||||
Contributed by Red Hat.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef GCC_RX_PROTOS_H
|
||||
#define GCC_RX_PROTOS_H
|
||||
|
||||
/* A few abbreviations to make the prototypes shorter. */
|
||||
#define Mmode enum machine_mode
|
||||
#define Fargs CUMULATIVE_ARGS
|
||||
|
||||
extern void rx_conditional_register_usage (void);
|
||||
extern void rx_expand_prologue (void);
|
||||
extern int rx_initial_elimination_offset (int, int);
|
||||
|
||||
#ifdef RTX_CODE
|
||||
extern void rx_emit_stack_popm (rtx *, bool);
|
||||
extern void rx_emit_stack_pushm (rtx *);
|
||||
extern void rx_expand_epilogue (bool);
|
||||
extern bool rx_expand_insv (rtx *);
|
||||
extern const char * rx_gen_cond_branch_template (rtx, bool);
|
||||
extern char * rx_gen_move_template (rtx *, bool);
|
||||
extern bool rx_is_legitimate_constant (rtx);
|
||||
extern bool rx_is_mode_dependent_addr (rtx);
|
||||
extern bool rx_is_restricted_memory_address (rtx, Mmode);
|
||||
extern void rx_notice_update_cc (rtx body, rtx insn);
|
||||
extern void rx_print_operand (FILE *, rtx, int);
|
||||
extern void rx_print_operand_address (FILE *, rtx);
|
||||
#endif
|
||||
|
||||
#ifdef TREE_CODE
|
||||
extern unsigned int rx_function_arg_size (Mmode, const_tree);
|
||||
extern struct rtx_def * rx_function_arg (Fargs *, Mmode, const_tree, bool);
|
||||
#endif
|
||||
|
||||
#endif /* GCC_RX_PROTOS_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,632 @@
|
|||
/* GCC backend definitions for the Renesas RX processor.
|
||||
Copyright (C) 2008, 2009 Free Software Foundation, Inc.
|
||||
Contributed by Red Hat.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
|
||||
#define TARGET_CPU_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_define ("__RX__"); \
|
||||
builtin_assert ("cpu=RX"); \
|
||||
builtin_assert ("machine=RX"); \
|
||||
\
|
||||
if (TARGET_BIG_ENDIAN_DATA) \
|
||||
builtin_define ("__RX_BIG_ENDIAN__"); \
|
||||
else \
|
||||
builtin_define ("__RX_LITTLE_ENDIAN__");\
|
||||
\
|
||||
if (TARGET_64BIT_DOUBLES) \
|
||||
builtin_define ("__RX_64BIT_DOUBLES__");\
|
||||
else \
|
||||
builtin_define ("__RX_32BIT_DOUBLES__");\
|
||||
\
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
builtin_define ("__RX_AS100_SYNTAX__"); \
|
||||
else \
|
||||
builtin_define ("__RX_GAS_SYNTAX__"); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#undef STARTFILE_SPEC
|
||||
#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
|
||||
|
||||
#undef ENDFILE_SPEC
|
||||
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
|
||||
|
||||
#undef ASM_SPEC
|
||||
#define ASM_SPEC "\
|
||||
%{mbig-endian-data:-mbig-endian-data} \
|
||||
%{m64bit-doubles:-m64bit-doubles} \
|
||||
%{msmall-data-limit*:-msmall-data-limit} \
|
||||
%{mrelax:-relax} \
|
||||
"
|
||||
|
||||
#undef LIB_SPEC
|
||||
#define LIB_SPEC " \
|
||||
--start-group \
|
||||
-lc \
|
||||
%{msim*:-lsim}%{!msim*:-lnosys} \
|
||||
%{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
|
||||
--end-group \
|
||||
%{!T*: %{msim*:%Trx-sim.ld}%{!msim*:%Trx.ld}} \
|
||||
"
|
||||
|
||||
#undef LINK_SPEC
|
||||
#define LINK_SPEC "%{mbig-endian-data:--oformat elf32-rx-be} %{mrelax:-relax}"
|
||||
|
||||
|
||||
#define BITS_BIG_ENDIAN 0
|
||||
#define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
|
||||
#define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
|
||||
|
||||
#ifdef __RX_BIG_ENDIAN__
|
||||
#define LIBGCC2_WORDS_BIG_ENDIAN 1
|
||||
#else
|
||||
#define LIBGCC2_WORDS_BIG_ENDIAN 0
|
||||
#endif
|
||||
|
||||
#define UNITS_PER_WORD 4
|
||||
|
||||
#define INT_TYPE_SIZE 32
|
||||
#define LONG_TYPE_SIZE 32
|
||||
#define LONG_LONG_TYPE_SIZE 64
|
||||
|
||||
#define FLOAT_TYPE_SIZE 32
|
||||
#define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32)
|
||||
#define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
|
||||
|
||||
#ifdef __RX_64BIT_DOUBLES__
|
||||
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
|
||||
#define LIBGCC2_DOUBLE_TYPE_SIZE 64
|
||||
#define LIBGCC2_HAS_DF_MODE 1
|
||||
#else
|
||||
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 32
|
||||
#define LIBGCC2_DOUBLE_TYPE_SIZE 32
|
||||
#endif
|
||||
|
||||
#define DEFAULT_SIGNED_CHAR 0
|
||||
|
||||
#define STRICT_ALIGNMENT 1
|
||||
#define FUNCTION_BOUNDARY 8
|
||||
#define BIGGEST_ALIGNMENT 32
|
||||
#define STACK_BOUNDARY 32
|
||||
#define PARM_BOUNDARY 8
|
||||
|
||||
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) 32
|
||||
|
||||
#define STACK_GROWS_DOWNWARD 1
|
||||
#define FRAME_GROWS_DOWNWARD 0
|
||||
#define FIRST_PARM_OFFSET(FNDECL) 0
|
||||
|
||||
#define MAX_REGS_PER_ADDRESS 2
|
||||
|
||||
#define Pmode SImode
|
||||
#define POINTER_SIZE 32
|
||||
#undef SIZE_TYPE
|
||||
#define SIZE_TYPE "long unsigned int"
|
||||
#define POINTERS_EXTEND_UNSIGNED 1
|
||||
#define FUNCTION_MODE QImode
|
||||
#define CASE_VECTOR_MODE Pmode
|
||||
#define WORD_REGISTER_OPERATIONS 1
|
||||
#define HAS_LONG_COND_BRANCH 0
|
||||
#define HAS_LONG_UNCOND_BRANCH 0
|
||||
|
||||
#define MOVE_MAX 4
|
||||
#define STARTING_FRAME_OFFSET 0
|
||||
|
||||
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
|
||||
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
||||
|
||||
#define LEGITIMATE_CONSTANT_P(X) rx_is_legitimate_constant (X)
|
||||
|
||||
#define HANDLE_PRAGMA_PACK_PUSH_POP 1
|
||||
|
||||
#define HAVE_PRE_DECCREMENT 1
|
||||
#define HAVE_POST_INCREMENT 1
|
||||
|
||||
#define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2)
|
||||
#define SLOW_BYTE_ACCESS 1
|
||||
|
||||
#define STORE_FLAG_VALUE 1
|
||||
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
|
||||
#define SHORT_IMMEDIATES_SIGN_EXTEND 1
|
||||
|
||||
enum reg_class
|
||||
{
|
||||
NO_REGS, /* No registers in set. */
|
||||
GR_REGS, /* Integer registers. */
|
||||
ALL_REGS, /* All registers. */
|
||||
LIM_REG_CLASSES /* Max value + 1. */
|
||||
};
|
||||
|
||||
#define REG_CLASS_NAMES \
|
||||
{ \
|
||||
"NO_REGS", \
|
||||
"GR_REGS", \
|
||||
"ALL_REGS" \
|
||||
}
|
||||
|
||||
#define REG_CLASS_CONTENTS \
|
||||
{ \
|
||||
{ 0x00000000 }, /* No registers, */ \
|
||||
{ 0x0000ffff }, /* Integer registers. */ \
|
||||
{ 0x0000ffff } /* All registers. */ \
|
||||
}
|
||||
|
||||
#define IRA_COVER_CLASSES \
|
||||
{ \
|
||||
GR_REGS, LIM_REG_CLASSES \
|
||||
}
|
||||
|
||||
#define SMALL_REGISTER_CLASSES 0
|
||||
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
||||
#define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
|
||||
+ UNITS_PER_WORD - 1) \
|
||||
/ UNITS_PER_WORD)
|
||||
|
||||
#define GENERAL_REGS GR_REGS
|
||||
#define BASE_REG_CLASS GR_REGS
|
||||
#define INDEX_REG_CLASS GR_REGS
|
||||
|
||||
#define FIRST_PSEUDO_REGISTER 16
|
||||
|
||||
#define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
|
||||
? GR_REGS : NO_REGS)
|
||||
|
||||
#define STACK_POINTER_REGNUM 0
|
||||
#define FUNC_RETURN_REGNUM 1
|
||||
#define FRAME_POINTER_REGNUM 6
|
||||
#define ARG_POINTER_REGNUM 7
|
||||
#define STATIC_CHAIN_REGNUM 8
|
||||
#define TRAMPOLINE_TEMP_REGNUM 9
|
||||
#define STRUCT_VAL_REGNUM 15
|
||||
|
||||
/* This is the register which is used to hold the address of the start
|
||||
of the small data area, if that feature is being used. Note - this
|
||||
register must not be call_used because otherwise library functions
|
||||
that are compiled without small data support might clobber it.
|
||||
|
||||
FIXME: The function gcc/config/rx/rx.c:rx_gen_move_template() has a
|
||||
built in copy of this register's name, rather than constructing the
|
||||
name from this #define. */
|
||||
#define GP_BASE_REGNUM 13
|
||||
|
||||
#define ELIMINABLE_REGS \
|
||||
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
||||
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
|
||||
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
|
||||
|
||||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||||
(OFFSET) = rx_initial_elimination_offset ((FROM), (TO))
|
||||
|
||||
|
||||
#define FUNCTION_ARG_REGNO_P(N) (((N) >= 1) && ((N) <= 4))
|
||||
#define FUNCTION_VALUE_REGNO_P(N) ((N) == FUNC_RETURN_REGNUM)
|
||||
#define DEFAULT_PCC_STRUCT_RETURN 0
|
||||
|
||||
#define FIXED_REGISTERS \
|
||||
{ \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
|
||||
}
|
||||
|
||||
#define CALL_USED_REGISTERS \
|
||||
{ \
|
||||
1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 \
|
||||
}
|
||||
|
||||
#define CONDITIONAL_REGISTER_USAGE \
|
||||
rx_conditional_register_usage ()
|
||||
|
||||
#define LIBCALL_VALUE(MODE) \
|
||||
gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
|
||||
|| GET_MODE_SIZE (MODE) >= 4) \
|
||||
? (MODE) \
|
||||
: SImode), \
|
||||
FUNC_RETURN_REGNUM)
|
||||
|
||||
/* Order of allocation of registers. */
|
||||
|
||||
#define REG_ALLOC_ORDER \
|
||||
{ 7, 10, 11, 12, 13, 14, 4, 3, 2, 1, 9, 8, 6, 5, 15 \
|
||||
}
|
||||
|
||||
#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
|
||||
|
||||
#define REGNO_IN_RANGE(REGNO, MIN, MAX) \
|
||||
(IN_RANGE ((REGNO), (MIN), (MAX)) \
|
||||
|| (reg_renumber != NULL \
|
||||
&& reg_renumber[(REGNO)] >= (MIN) \
|
||||
&& reg_renumber[(REGNO)] <= (MAX)))
|
||||
|
||||
#ifdef REG_OK_STRICT
|
||||
#define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 0, 15)
|
||||
#else
|
||||
#define REGNO_OK_FOR_BASE_P(regno) 1
|
||||
#endif
|
||||
|
||||
#define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
|
||||
|
||||
#define RTX_OK_FOR_BASE(X, STRICT) \
|
||||
((STRICT) ? \
|
||||
( (REG_P (X) \
|
||||
&& REGNO_IN_RANGE (REGNO (X), 0, 15)) \
|
||||
|| (GET_CODE (X) == SUBREG \
|
||||
&& REG_P (SUBREG_REG (X)) \
|
||||
&& REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \
|
||||
: \
|
||||
( (REG_P (X) \
|
||||
|| (GET_CODE (X) == SUBREG \
|
||||
&& REG_P (SUBREG_REG (X))))))
|
||||
|
||||
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
||||
do \
|
||||
{ \
|
||||
if (rx_is_mode_dependent_addr (ADDR)) \
|
||||
goto LABEL; \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
|
||||
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
|
||||
((COUNT) == 0 \
|
||||
? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT (-4))) \
|
||||
: NULL_RTX)
|
||||
|
||||
#define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
|
||||
|
||||
#define ACCUMULATE_OUTGOING_ARGS 1
|
||||
|
||||
typedef unsigned int CUMULATIVE_ARGS;
|
||||
|
||||
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
||||
(CUM) = 0
|
||||
|
||||
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
||||
rx_function_arg (& CUM, MODE, TYPE, NAMED)
|
||||
|
||||
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
||||
(CUM) += rx_function_arg_size (MODE, TYPE)
|
||||
|
||||
#define TRAMPOLINE_SIZE (! TARGET_BIG_ENDIAN_DATA ? 14 : 20)
|
||||
#define TRAMPOLINE_ALIGNMENT 32
|
||||
|
||||
#define NO_PROFILE_COUNTERS 1
|
||||
#define PROFILE_BEFORE_PROLOGUE 1
|
||||
|
||||
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
||||
fprintf (FILE, "\tbsr\t__mcount\n");
|
||||
|
||||
|
||||
#define HARD_REGNO_NREGS(REGNO, MODE) CLASS_MAX_NREGS (0, MODE)
|
||||
|
||||
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
||||
REGNO_REG_CLASS (REGNO) == GR_REGS
|
||||
|
||||
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
||||
( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|
||||
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
|
||||
== ( GET_MODE_CLASS (MODE2) == MODE_FLOAT \
|
||||
|| GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
|
||||
|
||||
|
||||
#define REGISTER_NAMES \
|
||||
{ \
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" \
|
||||
};
|
||||
|
||||
#define ADDITIONAL_REGISTER_NAMES \
|
||||
{ \
|
||||
{ "sp", STACK_POINTER_REGNUM } \
|
||||
, { "fp", FRAME_POINTER_REGNUM } \
|
||||
, { "arg", ARG_POINTER_REGNUM } \
|
||||
, { "chain", STATIC_CHAIN_REGNUM } \
|
||||
}
|
||||
|
||||
#define DATA_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION D,DATA" \
|
||||
: "\t.section D,\"aw\",@progbits\n\t.p2align 2")
|
||||
|
||||
#define SDATA_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION D_2,DATA,ALIGN=2" \
|
||||
: "\t.section D_2,\"aw\",@progbits\n\t.p2align 1")
|
||||
|
||||
#undef READONLY_DATA_SECTION_ASM_OP
|
||||
#define READONLY_DATA_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION C,ROMDATA,ALIGN=4" \
|
||||
: "\t.section C,\"a\",@progbits\n\t.p2align 2")
|
||||
|
||||
#define BSS_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION B,DATA,ALIGN=4" \
|
||||
: "\t.section B,\"w\",@nobits\n\t.p2align 2")
|
||||
|
||||
#define SBSS_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION B_2,DATA,ALIGN=2" \
|
||||
: "\t.section B_2,\"w\",@nobits\n\t.p2align 1")
|
||||
|
||||
/* The following definitions are conditional depending upon whether the
|
||||
compiler is being built or crtstuff.c is being compiled by the built
|
||||
compiler. */
|
||||
#if defined CRT_BEGIN || defined CRT_END
|
||||
# ifdef __RX_AS100_SYNTAX
|
||||
# define TEXT_SECTION_ASM_OP "\t.SECTION P,CODE"
|
||||
# define CTORS_SECTION_ASM_OP "\t.SECTION init_array,CODE"
|
||||
# define DTORS_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
|
||||
# define INIT_ARRAY_SECTION_ASM_OP "\t.SECTION init_array,CODE"
|
||||
# define FINI_ARRAY_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
|
||||
# else
|
||||
# define TEXT_SECTION_ASM_OP "\t.section P,\"ax\""
|
||||
# define CTORS_SECTION_ASM_OP \
|
||||
"\t.section\t.init_array,\"aw\",@init_array"
|
||||
# define DTORS_SECTION_ASM_OP \
|
||||
"\t.section\t.fini_array,\"aw\",@fini_array"
|
||||
# define INIT_ARRAY_SECTION_ASM_OP \
|
||||
"\t.section\t.init_array,\"aw\",@init_array"
|
||||
# define FINI_ARRAY_SECTION_ASM_OP \
|
||||
"\t.section\t.fini_array,\"aw\",@fini_array"
|
||||
# endif
|
||||
#else
|
||||
# define TEXT_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION P,CODE" : "\t.section P,\"ax\"")
|
||||
|
||||
# define CTORS_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
|
||||
: "\t.section\t.init_array,\"aw\",@init_array")
|
||||
|
||||
# define DTORS_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
|
||||
: "\t.section\t.fini_array,\"aw\",@fini_array")
|
||||
|
||||
# define INIT_ARRAY_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
|
||||
: "\t.section\t.init_array,\"aw\",@init_array")
|
||||
|
||||
# define FINI_ARRAY_SECTION_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
|
||||
: "\t.section\t.fini_array,\"aw\",@fini_array")
|
||||
#endif
|
||||
|
||||
#define GLOBAL_ASM_OP \
|
||||
(TARGET_AS100_SYNTAX ? "\t.GLB\t" : "\t.global\t")
|
||||
#define ASM_COMMENT_START " ;"
|
||||
#define ASM_APP_ON ""
|
||||
#define ASM_APP_OFF ""
|
||||
#define LOCAL_LABEL_PREFIX "L"
|
||||
#undef USER_LABEL_PREFIX
|
||||
#define USER_LABEL_PREFIX "_"
|
||||
|
||||
#define ASM_OUTPUT_ALIGN(STREAM, LOG) \
|
||||
do \
|
||||
{ \
|
||||
if ((LOG) == 0) \
|
||||
break; \
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
{ \
|
||||
if ((LOG) >= 2) \
|
||||
fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
|
||||
else \
|
||||
fprintf (STREAM, "\t.ALIGN 2\n"); \
|
||||
} \
|
||||
else \
|
||||
fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
||||
fprintf (FILE, TARGET_AS100_SYNTAX ? "\t.LWORD L%d\n" : "\t.long .L%d\n", \
|
||||
VALUE)
|
||||
|
||||
/* This is how to output an element of a case-vector that is relative.
|
||||
Note: The local label referenced by the "3b" below is emitted by
|
||||
the tablejump insn. */
|
||||
|
||||
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
||||
fprintf (FILE, TARGET_AS100_SYNTAX \
|
||||
? "\t.LWORD L%d - ?-\n" : "\t.long .L%d - 1b\n", VALUE)
|
||||
|
||||
#define ASM_OUTPUT_SIZE_DIRECTIVE(STREAM, NAME, SIZE) \
|
||||
do \
|
||||
{ \
|
||||
HOST_WIDE_INT size_ = (SIZE); \
|
||||
\
|
||||
/* The as100 assembler does not have an equivalent of the SVR4 \
|
||||
.size pseudo-op. */ \
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
break; \
|
||||
\
|
||||
fputs (SIZE_ASM_OP, STREAM); \
|
||||
assemble_name (STREAM, NAME); \
|
||||
fprintf (STREAM, ", " HOST_WIDE_INT_PRINT_DEC "\n", size_); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#define ASM_OUTPUT_MEASURED_SIZE(STREAM, NAME) \
|
||||
do \
|
||||
{ \
|
||||
/* The as100 assembler does not have an equivalent of the SVR4 \
|
||||
.size pseudo-op. */ \
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
break; \
|
||||
fputs (SIZE_ASM_OP, STREAM); \
|
||||
assemble_name (STREAM, NAME); \
|
||||
fputs (", .-", STREAM); \
|
||||
assemble_name (STREAM, NAME); \
|
||||
putc ('\n', STREAM); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#define ASM_OUTPUT_TYPE_DIRECTIVE(STREAM, NAME, TYPE) \
|
||||
do \
|
||||
{ \
|
||||
/* The as100 assembler does not have an equivalent of the SVR4 \
|
||||
.size pseudo-op. */ \
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
break; \
|
||||
fputs (TYPE_ASM_OP, STREAM); \
|
||||
assemble_name (STREAM, NAME); \
|
||||
fputs (", ", STREAM); \
|
||||
fprintf (STREAM, TYPE_OPERAND_FMT, TYPE); \
|
||||
putc ('\n', STREAM); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#undef ASM_GENERATE_INTERNAL_LABEL
|
||||
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
|
||||
do \
|
||||
{ \
|
||||
sprintf (LABEL, TARGET_AS100_SYNTAX ? "*%s%u" : "*.%s%u", \
|
||||
PREFIX, (unsigned) (NUM)); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#undef ASM_OUTPUT_EXTERNAL
|
||||
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
|
||||
do \
|
||||
{ \
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
targetm.asm_out.globalize_label (FILE, NAME); \
|
||||
default_elf_asm_output_external (FILE, DECL, NAME); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#undef ASM_OUTPUT_ALIGNED_COMMON
|
||||
#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
|
||||
do \
|
||||
{ \
|
||||
if (TARGET_AS100_SYNTAX) \
|
||||
{ \
|
||||
fprintf ((FILE), "\t.GLB\t"); \
|
||||
assemble_name ((FILE), (NAME)); \
|
||||
fprintf ((FILE), "\n"); \
|
||||
assemble_name ((FILE), (NAME)); \
|
||||
switch ((ALIGN) / BITS_PER_UNIT) \
|
||||
{ \
|
||||
case 4: \
|
||||
fprintf ((FILE), ":\t.BLKL\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
|
||||
(SIZE) / 4); \
|
||||
break; \
|
||||
case 2: \
|
||||
fprintf ((FILE), ":\t.BLKW\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
|
||||
(SIZE) / 2); \
|
||||
break; \
|
||||
default: \
|
||||
fprintf ((FILE), ":\t.BLKB\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
|
||||
(SIZE)); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
fprintf ((FILE), "%s", COMMON_ASM_OP); \
|
||||
assemble_name ((FILE), (NAME)); \
|
||||
fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
|
||||
(SIZE), (ALIGN) / BITS_PER_UNIT); \
|
||||
} \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#undef SKIP_ASM_OP
|
||||
#define SKIP_ASM_OP (TARGET_AS100_SYNTAX ? "\t.BLKB\t" : "\t.zero\t")
|
||||
|
||||
#undef ASM_OUTPUT_LIMITED_STRING
|
||||
#define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \
|
||||
do \
|
||||
{ \
|
||||
const unsigned char *_limited_str = \
|
||||
(const unsigned char *) (STR); \
|
||||
unsigned ch; \
|
||||
\
|
||||
fprintf ((FILE), TARGET_AS100_SYNTAX \
|
||||
? "\t.BYTE\t\"" : "\t.string\t\""); \
|
||||
\
|
||||
for (; (ch = *_limited_str); _limited_str++) \
|
||||
{ \
|
||||
int escape; \
|
||||
\
|
||||
switch (escape = ESCAPES[ch]) \
|
||||
{ \
|
||||
case 0: \
|
||||
putc (ch, (FILE)); \
|
||||
break; \
|
||||
case 1: \
|
||||
fprintf ((FILE), "\\%03o", ch); \
|
||||
break; \
|
||||
default: \
|
||||
putc ('\\', (FILE)); \
|
||||
putc (escape, (FILE)); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
fprintf ((FILE), TARGET_AS100_SYNTAX ? "\"\n\t.BYTE\t0\n" : "\"\n");\
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#undef IDENT_ASM_OP
|
||||
#define IDENT_ASM_OP (TARGET_AS100_SYNTAX \
|
||||
? "\t.END\t; Built by: ": "\t.ident\t")
|
||||
|
||||
/* For PIC put jump tables into the text section so that the offsets that
|
||||
they contain are always computed between two same-section symbols. */
|
||||
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
|
||||
|
||||
#define PRINT_OPERAND(FILE, X, CODE) \
|
||||
rx_print_operand (FILE, X, CODE)
|
||||
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
|
||||
rx_print_operand_address (FILE, ADDR)
|
||||
|
||||
|
||||
#define CC_NO_CARRY 0400
|
||||
#define NOTICE_UPDATE_CC(EXP, INSN) rx_notice_update_cc (EXP, INSN)
|
||||
|
||||
extern int rx_float_compare_mode;
|
||||
|
||||
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
|
||||
#define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
|
||||
|
||||
/* Like REG_P except that this macro is true for SET expressions. */
|
||||
#define SET_P(rtl) (GET_CODE (rtl) == SET)
|
||||
|
||||
#define CAN_DEBUG_WITHOUT_FP 1
|
||||
|
||||
/* The AS100 assembler does not support .leb128 and .uleb128, but
|
||||
the compiler-build-time configure tests will have enabled their
|
||||
use because GAS supports them. So default to generating STABS
|
||||
debug information instead of DWARF2 when generating AS100
|
||||
compatible output. */
|
||||
#undef PREFERRED_DEBUGGING_TYPE
|
||||
#define PREFERRED_DEBUGGING_TYPE (TARGET_AS100_SYNTAX \
|
||||
? DBX_DEBUG : DWARF2_DEBUG)
|
||||
|
||||
#undef CC1_SPEC
|
||||
#define CC1_SPEC "%{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}}"
|
||||
|
||||
/* For some unknown reason LTO compression is not working, at
|
||||
least on my local system. So set the default compression
|
||||
level to none, for now. */
|
||||
#define OVERRIDE_OPTIONS \
|
||||
do \
|
||||
{ \
|
||||
if (flag_lto_compression_level == -1) \
|
||||
flag_lto_compression_level = 0; \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* This macro is used to decide when RX FPU instructions can be used. */
|
||||
#define ALLOW_RX_FPU_INSNS flag_unsafe_math_optimizations
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,74 @@
|
|||
; Command line options for the Renesas RX port of GCC.
|
||||
; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
|
||||
; Contributed by Red Hat.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 3, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
;---------------------------------------------------
|
||||
|
||||
m64bit-doubles
|
||||
Target RejectNegative Mask(64BIT_DOUBLES)
|
||||
Store doubles in 64 bits.
|
||||
|
||||
m32bit-doubles
|
||||
Target RejectNegative InverseMask(64BIT_DOUBLES)
|
||||
Stores doubles in 32 bits. This is the default.
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
mbig-endian-data
|
||||
Target RejectNegative Mask(BIG_ENDIAN_DATA)
|
||||
Data is stored in big-endian format.
|
||||
|
||||
mlittle-endian-data
|
||||
Target RejectNegative InverseMask(BIG_ENDIAN_DATA)
|
||||
Data is stored in little-endian format. (Default).
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
msmall-data-limit=
|
||||
Target RejectNegative Joined UInteger Var(rx_small_data_limit) Init(0)
|
||||
Maximum size of global and static variables which can be placed into the small data area.
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
msim
|
||||
Target
|
||||
Use the simulator runtime.
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
mas100-syntax
|
||||
Target Mask(AS100_SYNTAX)
|
||||
Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatable syntax.
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
mrelax
|
||||
Target
|
||||
Enable linker relaxation.
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
mmax-constant-size=
|
||||
Target RejectNegative Joined UInteger Var(rx_max_constant_size) Init(0)
|
||||
Maximum size in bytes of constant values allowed as operands.
|
||||
|
||||
;---------------------------------------------------
|
||||
|
||||
mint-register=
|
||||
Target RejectNegative Joined UInteger Var(rx_interrupt_registers) Init(0)
|
||||
Specifies the number of registers to reserve for interrupt handlers.
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
# Makefile fragment for building GCC for the Renesas RX target.
|
||||
# Copyright (C) 2008, 2009 Free Software Foundation, Inc.
|
||||
# Contributed by Red Hat.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published
|
||||
# by the Free Software Foundation; either version 3, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful, but
|
||||
# WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
# the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public
|
||||
# License along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
# Enable multilibs:
|
||||
|
||||
MULTILIB_OPTIONS = m64bit-doubles mbig-endian-data
|
||||
MULTILIB_DIRNAMES = 64fp big-endian-data
|
||||
MULTILIB_MATCHES = m64bit-doubles=mieee
|
||||
MULTILIB_EXCEPTIONS =
|
||||
MULTILIB_EXTRA_OPTS =
|
||||
|
||||
LIBGCC = stmp-multilib
|
||||
INSTALL_LIBGCC = install-multilib
|
||||
|
||||
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
|
||||
|
|
@ -173,8 +173,8 @@ The @uref{http://www.gnu.org/software/classpath/,,GNU Classpath project}
|
|||
for all of their merged runtime code.
|
||||
|
||||
@item
|
||||
Nick Clifton for arm, mcore, fr30, v850, m32r work, @option{--help}, and
|
||||
other random hacking.
|
||||
Nick Clifton for arm, mcore, fr30, v850, m32r, rx work,
|
||||
@option{--help}, and other random hacking.
|
||||
|
||||
@item
|
||||
Michael Cook for libstdc++ cleanup patches to reduce warnings.
|
||||
|
|
|
|||
|
|
@ -2244,6 +2244,13 @@ on data in the eight bit data area. Note the eight bit data area is limited to
|
|||
You must use GAS and GLD from GNU binutils version 2.7 or later for
|
||||
this attribute to work correctly.
|
||||
|
||||
@item exception
|
||||
@cindex exception handler functions on the RX processor
|
||||
Use this attribute on the RX to indicate that the specified function
|
||||
is an exception handler. The compiler will generate function entry and
|
||||
exit sequences suitable for use in an exception handler when this
|
||||
attribute is present.
|
||||
|
||||
@item exception_handler
|
||||
@cindex exception handler functions on the Blackfin processor
|
||||
Use this attribute on the Blackfin to indicate that the specified function
|
||||
|
|
@ -2280,7 +2287,7 @@ addressing modes.
|
|||
|
||||
@item fast_interrupt
|
||||
@cindex interrupt handler functions
|
||||
Use this attribute on the M32C port to indicate that the specified
|
||||
Use this attribute on the M32C and RX ports to indicate that the specified
|
||||
function is a fast interrupt handler. This is just like the
|
||||
@code{interrupt} attribute, except that @code{freit} is used to return
|
||||
instead of @code{reit}.
|
||||
|
|
@ -2472,8 +2479,8 @@ This attribute is ignored for R8C target.
|
|||
|
||||
@item interrupt
|
||||
@cindex interrupt handler functions
|
||||
Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MeP, MIPS
|
||||
and Xstormy16 ports to indicate that the specified function is an
|
||||
Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MeP, MIPS,
|
||||
RX and Xstormy16 ports to indicate that the specified function is an
|
||||
interrupt handler. The compiler will generate function entry and exit
|
||||
sequences suitable for use in an interrupt handler when this attribute
|
||||
is present.
|
||||
|
|
@ -2689,7 +2696,7 @@ support for the swap suffix in the assembler. (GNU Binutils 2.19.51 or later)
|
|||
|
||||
@item naked
|
||||
@cindex function without a prologue/epilogue code
|
||||
Use this attribute on the ARM, AVR, IP2K and SPU ports to indicate that
|
||||
Use this attribute on the ARM, AVR, IP2K, RX and SPU ports to indicate that
|
||||
the specified function does not need prologue/epilogue sequences generated by
|
||||
the compiler. It is up to the programmer to provide these sequences. The
|
||||
only statements that can be safely included in naked functions are
|
||||
|
|
@ -7460,6 +7467,7 @@ instructions, but allow the compiler to schedule those calls.
|
|||
* Other MIPS Built-in Functions::
|
||||
* picoChip Built-in Functions::
|
||||
* PowerPC AltiVec/VSX Built-in Functions::
|
||||
* RX Built-in Functions::
|
||||
* SPARC VIS Built-in Functions::
|
||||
* SPU Built-in Functions::
|
||||
@end menu
|
||||
|
|
@ -11754,6 +11762,121 @@ long __builtin_bpermd (long, long);
|
|||
int __builtin_bswap16 (int);
|
||||
@end smallexample
|
||||
|
||||
@node RX Built-in Functions
|
||||
@subsection RX Built-in Functions
|
||||
GCC supports some of the RX instructions which cannot be expressed in
|
||||
the C programming language via the use of built-in functions. The
|
||||
following functions are supported:
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_brk (void)
|
||||
Generates the @code{brk} machine instruction.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_clrpsw (int)
|
||||
Generates the @code{clrpsw} machine instruction to clear the specified
|
||||
bit in the processor status word.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_int (int)
|
||||
Generates the @code{int} machine instruction to generate an interrupt
|
||||
with the specified value.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_machi (int, int)
|
||||
Generates the @code{machi} machine instruction to add the result of
|
||||
multiplying the top 16-bits of the two arguments into the
|
||||
accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_maclo (int, int)
|
||||
Generates the @code{maclo} machine instruction to add the result of
|
||||
multiplying the bottom 16-bits of the two arguments into the
|
||||
accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_mulhi (int, int)
|
||||
Generates the @code{mulhi} machine instruction to place the result of
|
||||
multiplying the top 16-bits of the two arguments into the
|
||||
accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_mullo (int, int)
|
||||
Generates the @code{mullo} machine instruction to place the result of
|
||||
multiplying the bottom 16-bits of the two arguments into the
|
||||
accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} int __builtin_rx_mvfachi (void)
|
||||
Generates the @code{mvfachi} machine instruction to read the top
|
||||
32-bits of the accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} int __builtin_rx_mvfacmi (void)
|
||||
Generates the @code{mvfacmi} machine instruction to read the middle
|
||||
32-bits of the accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} int __builtin_rx_mvfc (int)
|
||||
Generates the @code{mvfc} machine instruction which reads the control
|
||||
register specified in its argument and returns its value.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_mvtachi (int)
|
||||
Generates the @code{mvtachi} machine instruction to set the top
|
||||
32-bits of the accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_mvtaclo (int)
|
||||
Generates the @code{mvtaclo} machine instruction to set the bottom
|
||||
32-bits of the accumulator.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_mvtc (int reg, int val)
|
||||
Generates the @code{mvtc} machine instruction which sets control
|
||||
register number @code{reg} to @code{val}.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_mvtipl (int)
|
||||
Generates the @code{mvtipl} machine instruction set the interrupt
|
||||
priority level.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_racw (int)
|
||||
Generates the @code{racw} machine instruction to round the accumulator
|
||||
according to the specified mode.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} int __builtin_rx_revw (int)
|
||||
Generates the @code{revw} machine instruction which swaps the bytes in
|
||||
the argument so that bits 0--7 now occupy bits 8--15 and vice versa,
|
||||
and also bits 16--23 occupy bits 24--31 and vice versa.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_rmpa (void)
|
||||
Generates the @code{rmpa} machine instruction which initiates a
|
||||
repeated multiply and accumulate sequence.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_round (float)
|
||||
Generates the @code{round} machine instruction which returns the
|
||||
floating point argument rounded according to the current rounding mode
|
||||
set in the floating point status word register.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} int __builtin_rx_sat (int)
|
||||
Generates the @code{sat} machine instruction which returns the
|
||||
saturated value of the argument.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_setpsw (int)
|
||||
Generates the @code{setpsw} machine instruction to set the specified
|
||||
bit in the processor status word.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} void __builtin_rx_wait (void)
|
||||
Generates the @code{wait} machine instruction.
|
||||
@end deftypefn
|
||||
|
||||
@node SPARC VIS Built-in Functions
|
||||
@subsection SPARC VIS Built-in Functions
|
||||
|
||||
|
|
@ -12003,7 +12126,6 @@ extern int foo ();
|
|||
|
||||
@end table
|
||||
|
||||
|
||||
@node RS/6000 and PowerPC Pragmas
|
||||
@subsection RS/6000 and PowerPC Pragmas
|
||||
|
||||
|
|
|
|||
|
|
@ -4001,6 +4001,14 @@ the PSIM simulator.
|
|||
@heading @anchor{powerpcle-x-eabi}powerpcle-*-eabi
|
||||
Embedded PowerPC system in little endian mode.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
@heading @anchor{rx-x-elf}rx-*-elf
|
||||
The Renesas RX processor. See
|
||||
@uref{http://eu.renesas.com/fmwk.jsp?cnt=rx600_series_landing.jsp&fp=/products/mpumcu/rx_family/rx600_series}
|
||||
for more information about this processor.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
|
|
|
|||
|
|
@ -783,6 +783,16 @@ See RS/6000 and PowerPC Options.
|
|||
-msim -mmvme -mads -myellowknife -memb -msdata @gol
|
||||
-msdata=@var{opt} -mvxworks -G @var{num} -pthread}
|
||||
|
||||
@emph{RX Options}
|
||||
@gccoptlist{-m64bit-doubles -m32bit-doubles -mieee -mno-ieee@gol
|
||||
-mbig-endian-data -mlittle-endian-data @gol
|
||||
-msmall-data @gol
|
||||
-msim -mno-sim@gol
|
||||
-mas100-syntax -mno-as100-syntax@gol
|
||||
-mrelax@gol
|
||||
-mmax-constant-size=@gol
|
||||
-mint-register=}
|
||||
|
||||
@emph{S/390 and zSeries Options}
|
||||
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
|
||||
-mhard-float -msoft-float -mhard-dfp -mno-hard-dfp @gol
|
||||
|
|
@ -9530,6 +9540,7 @@ platform.
|
|||
* picoChip Options::
|
||||
* PowerPC Options::
|
||||
* RS/6000 and PowerPC Options::
|
||||
* RX Options::
|
||||
* S/390 and zSeries Options::
|
||||
* Score Options::
|
||||
* SH Options::
|
||||
|
|
@ -10943,7 +10954,7 @@ These @samp{-m} options are defined for the DEC Alpha/VMS implementations:
|
|||
@table @gcctabopt
|
||||
@item -mvms-return-codes
|
||||
@opindex mvms-return-codes
|
||||
Return VMS condition codes from main. The default is to return POSIX
|
||||
Return VMS condition codes from main. The default is to return POSIX
|
||||
style condition (e.g.@: error) codes.
|
||||
|
||||
@item -mdebug-main=@var{prefix}
|
||||
|
|
@ -15362,6 +15373,112 @@ This option sets flags for both the preprocessor and linker.
|
|||
|
||||
@end table
|
||||
|
||||
@node RX Options
|
||||
@subsection RX Options
|
||||
@cindex RX Options
|
||||
|
||||
These @option{-m} options are defined for RX implementations:
|
||||
|
||||
@table @gcctabopt
|
||||
@item -m64bit-doubles
|
||||
@itemx -m32bit-doubles
|
||||
@opindex m64bit-doubles
|
||||
@opindex m32bit-doubles
|
||||
Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
|
||||
or 32-bits (@option{-m32bit-doubles}) in size. The default is
|
||||
@option{-m32bit-doubles}. @emph{Note} the RX's hardware floating
|
||||
point instructions are only used for 32-bit floating point values, and
|
||||
then only if @option{-ffast-math} has been specified on the command
|
||||
line. This is because the RX FPU instructions do not properly support
|
||||
denormal (or sub-normal) values.
|
||||
|
||||
@item -mbig-endian-data
|
||||
@itemx -mlittle-endian-data
|
||||
@opindex mbig-endian-data
|
||||
@opindex mlittle-endian-data
|
||||
Store data (but not code) in the big-endian format. The default is
|
||||
@option{-mlittle-endian-data}, ie to store data in the little endian
|
||||
format.
|
||||
|
||||
@item -msmall-data-limit=@var{N}
|
||||
@opindex msmall-data-limit
|
||||
Specifies the maximum size in bytes of global and static variables
|
||||
which can be placed into the small data area. Using the small data
|
||||
area can lead to smaller and faster code, but the size of area is
|
||||
limited and it is up to the programmer to ensure that the area does
|
||||
not overflow. Also when the small data area is used one of the RX's
|
||||
registers (@code{r13}) is reserved for use pointing to this area, so
|
||||
it is no longer available for use by the compiler. This could result
|
||||
in slower and/or larger code if variables which once could have been
|
||||
held in @code{r13} are now pushed onto the stack.
|
||||
|
||||
Note, common variables (variables which have not been initialised) and
|
||||
constants are not placed into the small data area as they are assigned
|
||||
to other sections in the output executeable.
|
||||
|
||||
The default value is zero, which disables this feature. Note, this
|
||||
feature is not enabled by default with higher optimization levels
|
||||
(@option{-O2} etc) because of the potentially deterimental effects of
|
||||
reserving register @code{r13}. It is up to the programmer to
|
||||
experiment and discover whether this feature is of benefit to their
|
||||
program.
|
||||
|
||||
@item -msim
|
||||
@item -mno-sim
|
||||
@opindex msim
|
||||
@opindex mno-sim
|
||||
Use the simulator runtime. The default is to use the libgloss board
|
||||
specific runtime.
|
||||
|
||||
@item -mas100-syntax
|
||||
@item -mno-as100-syntax
|
||||
@opindex mas100-syntax
|
||||
@opindex mno-as100-syntax
|
||||
When generating assembler output use a syntax that is compatible with
|
||||
Renesas's AS100 assembler. This syntax can also be handled by the GAS
|
||||
assembler but it has some restrictions so generating it is not the
|
||||
default option.
|
||||
|
||||
@item -mmax-constant-size=@var{N}
|
||||
@opindex mmax-constant-size
|
||||
Specifies the maxium size, in bytes, of a constant that can be used as
|
||||
an operand in a RX instruction. Although the RX instruction set does
|
||||
allow consants of up to 4 bytes in length to be used in instructions,
|
||||
a longer value equates to a longer instruction. Thus in some
|
||||
circumstances it can be beneficial to restrict the size of constants
|
||||
that are used in instructions. Constants that are too big are instead
|
||||
placed into a constant pool and referenced via register indirection.
|
||||
|
||||
The value @var{N} can be between 0 and 3. A value of 0, the default,
|
||||
means that constants of any size are allowed.
|
||||
|
||||
@item -mrelax
|
||||
@opindex mrelax
|
||||
Enable linker relaxation. Linker relaxation is a process whereby the
|
||||
linker will attempt to reduce the size of a program by finding shorter
|
||||
versions of various instructions. Disabled by default.
|
||||
|
||||
@item -mint-register=@var{N}
|
||||
@opindex mint-register
|
||||
Specify the number of registers to reserve for fast interrupt handler
|
||||
functions. The value @var{N} can be between 0 and 4. A value of 1
|
||||
means that register @code{r13} will be reserved for ther exclusive use
|
||||
of fast interrupt handlers. A value of 2 reserves @code{r13} and
|
||||
@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and
|
||||
@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
|
||||
A value of 0, the default, does not reserve any registers.
|
||||
@end table
|
||||
|
||||
@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}
|
||||
has special significance to the RX port when used with the
|
||||
@code{interrupt} function attribute. This attribute indicates a
|
||||
function intended to process fast interrupts. GCC will will ensure
|
||||
that it only uses the registers @code{r10}, @code{r11}, @code{r12}
|
||||
and/or @code{r13} and only provided that the normal use of the
|
||||
corresponding registers have been restricted via the
|
||||
@option{-ffixed-@var{reg}} or @option{-mint-register} command line
|
||||
options.
|
||||
|
||||
@node S/390 and zSeries Options
|
||||
@subsection S/390 and zSeries Options
|
||||
@cindex S/390 and zSeries Options
|
||||
|
|
|
|||
|
|
@ -2897,6 +2897,32 @@ A constant in the range of 0 to @minus{}255.
|
|||
|
||||
@end table
|
||||
|
||||
@item RX---@file{config/rx/constraints.md}
|
||||
@table @code
|
||||
@item Q
|
||||
An address which does not involve register indirect addressing or
|
||||
pre/post increment/decrement addressing.
|
||||
|
||||
@item Symbol
|
||||
A symbol reference.
|
||||
|
||||
@item Int08
|
||||
A constant in the range @minus{}256 to 255, inclusive.
|
||||
|
||||
@item Sint08
|
||||
A constant in the range @minus{}128 to 127, inclusive.
|
||||
|
||||
@item Sint16
|
||||
A constant in the range @minus{}32768 to 32767, inclusive.
|
||||
|
||||
@item Sint24
|
||||
A constant in the range @minus{}8388608 to 8388607, inclusive.
|
||||
|
||||
@item Uint04
|
||||
A constant in the range 0 to 15, inclusive.
|
||||
|
||||
@end table
|
||||
|
||||
@need 1000
|
||||
@item SPARC---@file{config/sparc/sparc.h}
|
||||
@table @code
|
||||
|
|
|
|||
|
|
@ -3529,7 +3529,7 @@ dynamically if their size exceeds @code{STACK_CHECK_MAX_VAR_SIZE} bytes.
|
|||
@defmac STACK_CHECK_BUILTIN
|
||||
A nonzero value if stack checking is done by the configuration files in a
|
||||
machine-dependent manner. You should define this macro if stack checking
|
||||
is require by the ABI of your machine or if you would like to do stack
|
||||
is required by the ABI of your machine or if you would like to do stack
|
||||
checking in some more efficient way than the generic approach. The default
|
||||
value of this macro is zero.
|
||||
@end defmac
|
||||
|
|
@ -3788,7 +3788,7 @@ registers @code{regs_ever_live} and @code{call_used_regs}.
|
|||
|
||||
If @code{ELIMINABLE_REGS} is defined, this macro will be not be used and
|
||||
need not be defined. Otherwise, it must be defined even if
|
||||
@code{TARGET_FRAME_POINTER_REQUIRED} is always return true; in that
|
||||
@code{TARGET_FRAME_POINTER_REQUIRED} always returns true; in that
|
||||
case, you may set @var{depth-var} to anything.
|
||||
@end defmac
|
||||
|
||||
|
|
@ -4205,7 +4205,6 @@ on the stack. The compiler knows how to track the amount of stack space
|
|||
used for arguments without any special help.
|
||||
@end defmac
|
||||
|
||||
|
||||
@defmac FUNCTION_ARG_OFFSET (@var{mode}, @var{type})
|
||||
If defined, a C expression that is the number of bytes to add to the
|
||||
offset of the argument passed in memory. This is needed for the SPU,
|
||||
|
|
@ -5370,9 +5369,10 @@ post-address side-effect generation involving a register displacement.
|
|||
|
||||
@defmac CONSTANT_ADDRESS_P (@var{x})
|
||||
A C expression that is 1 if the RTX @var{x} is a constant which
|
||||
is a valid address. On most machines, this can be defined as
|
||||
@code{CONSTANT_P (@var{x})}, but a few machines are more restrictive
|
||||
in which constant addresses are supported.
|
||||
is a valid address. On most machines the default definition of
|
||||
@code{(CONSTANT_P (@var{x}) && GET_CODE (@var{x}) != CONST_DOUBLE)}
|
||||
is acceptable, but a few machines are more restrictive as to which
|
||||
constant addresses are supported.
|
||||
@end defmac
|
||||
|
||||
@defmac CONSTANT_P (@var{x})
|
||||
|
|
@ -6127,7 +6127,7 @@ this macro is defined, it should produce a nonzero value when
|
|||
@code{STRICT_ALIGNMENT} is nonzero.
|
||||
@end defmac
|
||||
|
||||
@defmac MOVE_RATIO
|
||||
@defmac MOVE_RATIO (@var{speed})
|
||||
The threshold of number of scalar memory-to-memory move insns, @emph{below}
|
||||
which a sequence of insns should be generated instead of a
|
||||
string move insn or a library call. Increasing the value will always
|
||||
|
|
@ -6137,6 +6137,9 @@ Note that on machines where the corresponding move insn is a
|
|||
@code{define_expand} that emits a sequence of insns, this macro counts
|
||||
the number of such sequences.
|
||||
|
||||
The parameter @var{speed} is true if the code is currently being
|
||||
optimized for speed rather than size.
|
||||
|
||||
If you don't define this, a reasonable default is used.
|
||||
@end defmac
|
||||
|
||||
|
|
@ -6152,12 +6155,15 @@ A C expression used by @code{move_by_pieces} to determine the largest unit
|
|||
a load or store used to copy memory is. Defaults to @code{MOVE_MAX}.
|
||||
@end defmac
|
||||
|
||||
@defmac CLEAR_RATIO
|
||||
@defmac CLEAR_RATIO (@var{speed})
|
||||
The threshold of number of scalar move insns, @emph{below} which a sequence
|
||||
of insns should be generated to clear memory instead of a string clear insn
|
||||
or a library call. Increasing the value will always make code faster, but
|
||||
eventually incurs high cost in increased code size.
|
||||
|
||||
The parameter @var{speed} is true if the code is currently being
|
||||
optimized for speed rather than size.
|
||||
|
||||
If you don't define this, a reasonable default is used.
|
||||
@end defmac
|
||||
|
||||
|
|
@ -6168,13 +6174,16 @@ will be used. Defaults to 1 if @code{move_by_pieces_ninsns} returns less
|
|||
than @code{CLEAR_RATIO}.
|
||||
@end defmac
|
||||
|
||||
@defmac SET_RATIO
|
||||
@defmac SET_RATIO (@var{speed})
|
||||
The threshold of number of scalar move insns, @emph{below} which a sequence
|
||||
of insns should be generated to set memory to a constant value, instead of
|
||||
a block set insn or a library call.
|
||||
Increasing the value will always make code faster, but
|
||||
eventually incurs high cost in increased code size.
|
||||
|
||||
The parameter @var{speed} is true if the code is currently being
|
||||
optimized for speed rather than size.
|
||||
|
||||
If you don't define this, it defaults to the value of @code{MOVE_RATIO}.
|
||||
@end defmac
|
||||
|
||||
|
|
@ -6189,7 +6198,7 @@ than @code{SET_RATIO}.
|
|||
|
||||
@defmac STORE_BY_PIECES_P (@var{size}, @var{alignment})
|
||||
A C expression used to determine whether @code{store_by_pieces} will be
|
||||
used to set a chunk of memory to a constant string value, or whether some
|
||||
used to set a chunk of memory to a constant string value, or whether some
|
||||
other mechanism will be used. Used by @code{__builtin_strcpy} when
|
||||
called with a constant source string.
|
||||
Defaults to 1 if @code{move_by_pieces_ninsns} returns less
|
||||
|
|
@ -6255,7 +6264,7 @@ Define this macro if a non-short-circuit operation produced by
|
|||
@code{BRANCH_COST} is greater than or equal to the value 2.
|
||||
@end defmac
|
||||
|
||||
@deftypefn {Target Hook} bool TARGET_RTX_COSTS (rtx @var{x}, int @var{code}, int @var{outer_code}, int *@var{total})
|
||||
@deftypefn {Target Hook} bool TARGET_RTX_COSTS (rtx @var{x}, int @var{code}, int @var{outer_code}, int *@var{total}, bool @var{speed})
|
||||
This target hook describes the relative costs of RTL expressions.
|
||||
|
||||
The cost may depend on the precise form of the expression, which is
|
||||
|
|
@ -6274,15 +6283,15 @@ necessary. Traditionally, the default costs are @code{COSTS_N_INSNS (5)}
|
|||
for multiplications, @code{COSTS_N_INSNS (7)} for division and modulus
|
||||
operations, and @code{COSTS_N_INSNS (1)} for all other operations.
|
||||
|
||||
When optimizing for code size, i.e.@: when @code{optimize_size} is
|
||||
nonzero, this target hook should be used to estimate the relative
|
||||
When optimizing for code size, i.e.@: when @code{speed} is
|
||||
false, this target hook should be used to estimate the relative
|
||||
size cost of an expression, again relative to @code{COSTS_N_INSNS}.
|
||||
|
||||
The hook returns true when all subexpressions of @var{x} have been
|
||||
processed, and false when @code{rtx_cost} should recurse.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} int TARGET_ADDRESS_COST (rtx @var{address})
|
||||
@deftypefn {Target Hook} int TARGET_ADDRESS_COST (rtx @var{address}, bool @var{speed})
|
||||
This hook computes the cost of an addressing mode that contains
|
||||
@var{address}. If not defined, the cost is computed from
|
||||
the @var{address} expression and the @code{TARGET_RTX_COST} hook.
|
||||
|
|
@ -6384,7 +6393,7 @@ debug output to. @var{verbose} is the verbose level provided by
|
|||
list of instructions that are ready to be scheduled. @var{n_readyp} is
|
||||
a pointer to the number of elements in the ready list. The scheduler
|
||||
reads the ready list in reverse order, starting with
|
||||
@var{ready}[@var{*n_readyp}-1] and going to @var{ready}[0]. @var{clock}
|
||||
@var{ready}[@var{*n_readyp} @minus{} 1] and going to @var{ready}[0]. @var{clock}
|
||||
is the timer tick of the scheduler. You may modify the ready list and
|
||||
the number of ready insns. The return value is the number of insns that
|
||||
can issue this cycle; normally this is just @code{issue_rate}. See also
|
||||
|
|
@ -9516,7 +9525,7 @@ attributes, or a copy of the list may be made if further changes are
|
|||
needed.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} bool TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P (tree @var{fndecl})
|
||||
@deftypefn {Target Hook} bool TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P (const_tree @var{fndecl})
|
||||
@cindex inlining
|
||||
This target hook returns @code{true} if it is ok to inline @var{fndecl}
|
||||
into the current function, despite its having target-specific
|
||||
|
|
@ -10910,7 +10919,6 @@ to the stack. Therefore, this hook should return true in general, but
|
|||
false for naked functions. The default implementation always returns true.
|
||||
@end deftypefn
|
||||
|
||||
|
||||
@deftypevr {Target Hook} {unsigned HOST_WIDE_INT} TARGET_CONST_ANCHOR
|
||||
On some architectures it can take multiple instructions to synthesize
|
||||
a constant. If there is another constant already in a register that
|
||||
|
|
|
|||
|
|
@ -1,3 +1,18 @@
|
|||
2009-10-26 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* lib/target-supports.exp (check_profiling_available):
|
||||
Profiling is not, currently, available for the RX port.
|
||||
(check_effective_target_hard_float): Add support for RX
|
||||
target.
|
||||
* gcc.target/rx: New directory.
|
||||
* gcc.target/rx/builtins.c: New test file.
|
||||
* gcc.target/rx/interrupts.c: New test file.
|
||||
* gcc.target/rx/rx-abi-function-tests.c: New test file.
|
||||
* gcc.target/rx/zero-width-bitfield.c: New test file.
|
||||
* gcc.target/rx/i272091.c: New test file.
|
||||
* gcc.target/rx/packed-struct.c: New test file.
|
||||
* gcc.target/rx/rx.exp: New file: Drives RX tests.
|
||||
|
||||
2009-10-26 Andrew Pinski <pinskia@gcc.gnu.org>
|
||||
|
||||
* gcc.dg/lto/20091014-1_0.c: Replace -shared with -r -nostlib.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,159 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-fno-ipa-cp-clone" } */
|
||||
|
||||
/* Verify that the RX specific builtin functions work. */
|
||||
|
||||
/* IPA CP cloning is disabled because the constant propagation
|
||||
has no understanding of the saturation behaviour of the
|
||||
__builtin_rx_sat function and so it will optimize away the
|
||||
saturation addition test. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
/* We need to prevent these functions from being inlined
|
||||
as otherwise gcc will attempt to optimize away their
|
||||
arguments and we need the operations on them in order
|
||||
to correctly set the psw flags. */
|
||||
|
||||
int saturate_add (int, int) __attribute__((__noinline__));
|
||||
int subtract_with_borrow (int, int, int) __attribute__((__noinline__));
|
||||
int exchange (int, int) __attribute__((__noinline__));
|
||||
|
||||
int
|
||||
half_word_swap (int arg)
|
||||
{
|
||||
return __builtin_rx_revw (arg);
|
||||
}
|
||||
|
||||
int
|
||||
saturate_add (int arg1, int arg2)
|
||||
{
|
||||
arg1 += arg2;
|
||||
return __builtin_rx_sat (arg1);
|
||||
}
|
||||
|
||||
long
|
||||
multiply_and_accumulate (long arg1, long arg2, long arg3)
|
||||
{
|
||||
__builtin_rx_mvtaclo (0);
|
||||
__builtin_rx_mvtachi (0);
|
||||
|
||||
__builtin_rx_mullo (arg1, arg2);
|
||||
__builtin_rx_mulhi (arg1, arg2);
|
||||
__builtin_rx_maclo (arg1, arg3);
|
||||
__builtin_rx_machi (arg1, arg3);
|
||||
|
||||
__builtin_rx_racw (1);
|
||||
|
||||
arg1 = __builtin_rx_mvfachi ();
|
||||
arg1 += __builtin_rx_mvfacmi ();
|
||||
|
||||
return arg1;
|
||||
}
|
||||
|
||||
int
|
||||
rxround (float arg)
|
||||
{
|
||||
return __builtin_rx_round (arg);
|
||||
}
|
||||
|
||||
/* #define DEBUG 1 */
|
||||
|
||||
#ifdef DEBUG
|
||||
#define CHECK_0ARG(func, result) \
|
||||
if (func () != result) \
|
||||
{ \
|
||||
printf (#func " () fails: %x not %x\n", func (), result); \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
#define CHECK_1ARG(func, arg, result) \
|
||||
if (func (arg) != result) \
|
||||
{ \
|
||||
printf (#func " (" #arg ") fails: %x not %x\n", func (arg), result); \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
#define CHECK_2ARG(func, arg1, arg2, result) \
|
||||
if (func (arg1, arg2) != result) \
|
||||
{ \
|
||||
printf (#func " (" #arg1 "," #arg2 ") fails: %x not %x\n", \
|
||||
func (arg1, arg2), result); \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
#define CHECK_3ARG(func, arg1, arg2, arg3, result) \
|
||||
if (func (arg1, arg2, arg3) != result) \
|
||||
{ \
|
||||
printf (#func " (" #arg1 "," #arg2 "," #arg3 ") fails: %x not %x\n", \
|
||||
func (arg1, arg2, arg3), result); \
|
||||
abort (); \
|
||||
}
|
||||
#else
|
||||
#define CHECK_0ARG(func, result) \
|
||||
if (func () != result) \
|
||||
abort ();
|
||||
|
||||
#define CHECK_1ARG(func, arg, result) \
|
||||
if (func (arg) != result) \
|
||||
abort ();
|
||||
|
||||
#define CHECK_2ARG(func, arg1, arg2, result) \
|
||||
if (func (arg1, arg2) != result) \
|
||||
abort ();
|
||||
|
||||
#define CHECK_3ARG(func, arg1, arg2, arg3, result) \
|
||||
if (func (arg1, arg2, arg3) != result) \
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
CHECK_1ARG (half_word_swap, 0x12345678, 0x34127856);
|
||||
CHECK_2ARG (saturate_add, 0x80000000, 0x80000000, 0x80000000);
|
||||
CHECK_3ARG (multiply_and_accumulate, 0x111, 0x222, 0x333, 0x70007);
|
||||
CHECK_1ARG (rxround, 0.5, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* The following builtins are compiled but
|
||||
not executed because they need OS support. */
|
||||
|
||||
void
|
||||
rxbreak (void)
|
||||
{
|
||||
__builtin_rx_brk ();
|
||||
}
|
||||
|
||||
void
|
||||
interrupt (void)
|
||||
{
|
||||
__builtin_rx_int (0x12);
|
||||
}
|
||||
|
||||
int
|
||||
get_stack_pointer (void)
|
||||
{
|
||||
return __builtin_rx_mvfc (2);
|
||||
}
|
||||
|
||||
void
|
||||
set_stack_pointer (int value)
|
||||
{
|
||||
__builtin_rx_mvtc (2, value);
|
||||
__builtin_rx_mvtc (2, 0x1234);
|
||||
}
|
||||
|
||||
void
|
||||
wait (void)
|
||||
{
|
||||
__builtin_rx_wait ();
|
||||
}
|
||||
|
||||
void
|
||||
rmpa (int * multiplicand, int * multiplier, int num)
|
||||
{
|
||||
__builtin_rx_rmpa ();
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-msmall-data-limit=100" } */
|
||||
|
||||
double a=6.76,b=7.34,c=0.54;
|
||||
double x_1= 45.46;
|
||||
static double SD_1;
|
||||
static double SD_init = 45.54;
|
||||
double DD_1;
|
||||
double DD_init=769.0;
|
||||
|
||||
|
||||
int main()
|
||||
{
|
||||
volatile double x,y,z;
|
||||
|
||||
x = 56.76;
|
||||
y = 4.5645;
|
||||
|
||||
z = x + y;
|
||||
z = x - 4.65;
|
||||
z = 4.566 - x;
|
||||
z = x * y;
|
||||
b = 8;
|
||||
c = 34;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mint-register=3" } */
|
||||
|
||||
/* Verify that the RX specific function attributes work. */
|
||||
|
||||
void interrupt (void) __attribute__((__interrupt__));
|
||||
void exception (void) __attribute__((__exception__));
|
||||
int naked (int) __attribute__((__naked__));
|
||||
|
||||
int flag = 0;
|
||||
|
||||
/* Fast interrupt handler. Only uses registers marked as fixed
|
||||
by the -fixed-xxx gcc command line option. Returns via RTFI. */
|
||||
|
||||
void
|
||||
interrupt (void)
|
||||
{
|
||||
flag = 1;
|
||||
}
|
||||
|
||||
/* Exception handler. Must preserve any register it uses, even
|
||||
call clobbered ones. Returns via RTE. */
|
||||
|
||||
void
|
||||
exception (void)
|
||||
{
|
||||
switch (flag)
|
||||
{
|
||||
case 0:
|
||||
flag = -1;
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
flag = flag - 2;
|
||||
break;
|
||||
case 5:
|
||||
case 7:
|
||||
case 6:
|
||||
flag ^= 3;
|
||||
break;
|
||||
default:
|
||||
naked (flag * 2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Naked function. The programmer must supply the function's
|
||||
prologue and epilogue instructions. */
|
||||
|
||||
int
|
||||
naked (int arg)
|
||||
{
|
||||
flag = arg;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "rtfi" } } */
|
||||
/* { dg-final { scan-assembler "rte" } } */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* { dg-do compile } */
|
||||
|
||||
struct unpacked
|
||||
{
|
||||
int i;
|
||||
char c;
|
||||
};
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
struct packed
|
||||
{
|
||||
int i;
|
||||
char c;
|
||||
};
|
||||
|
||||
struct packed_contains_unpacked
|
||||
{
|
||||
char c;
|
||||
struct unpacked uuuu; /* This should generate an error message. */
|
||||
}; /* { dg-error "unpacked structure/union inside a packed struct" "XFAILed until patch for generic GCC structure layout code is accepted" { xfail rx-*-* } } */
|
||||
|
||||
union contains_unpacked
|
||||
{
|
||||
char c;
|
||||
struct unpacked uuuu; /* This should not. */
|
||||
};
|
||||
|
||||
struct packed_contains_packed
|
||||
{
|
||||
char c;
|
||||
struct packed ppppp; /* This should not. */
|
||||
};
|
||||
|
||||
#pragma pack()
|
||||
|
||||
struct unpacked_contains_packed
|
||||
{
|
||||
char c;
|
||||
struct packed p;
|
||||
};
|
||||
|
||||
struct unpacked_contains_unpacked
|
||||
{
|
||||
char c;
|
||||
struct unpacked u;
|
||||
};
|
||||
|
||||
|
||||
int s1 = sizeof (struct unpacked);
|
||||
int s2 = sizeof (struct packed);
|
||||
int s3 = sizeof (struct packed_contains_unpacked);
|
||||
int s4 = sizeof (struct packed_contains_packed);
|
||||
int s5 = sizeof (struct unpacked_contains_packed);
|
||||
int s6 = sizeof (struct unpacked_contains_unpacked);
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-msim" } */
|
||||
/* Note: The -msim abiove is actually there to override the default
|
||||
options which include -ansi -pendantic and -Wlong-long... */
|
||||
|
||||
extern int printf (const char *, ...);
|
||||
extern void exit (int);
|
||||
extern void abort (void);
|
||||
|
||||
extern signed long _COM_CONVf32s (float);
|
||||
extern unsigned long _COM_CONVf32u (float);
|
||||
extern float _COM_CONV32sf (signed long);
|
||||
extern float _COM_CONV32uf (unsigned long);
|
||||
extern float _COM_ADDf (float, float);
|
||||
extern float _COM_SUBf (float, float);
|
||||
extern float _COM_MULf (float, float);
|
||||
extern float _COM_DIVf (float, float);
|
||||
extern int _COM_CMPLTf (float, float);
|
||||
|
||||
extern long long _COM_MUL64 (long long, long long);
|
||||
extern signed long long _COM_DIV64s (long long, long long);
|
||||
extern unsigned long long _COM_DIV64u (unsigned long long, unsigned long long);
|
||||
extern long long _COM_SHLL64 (long long, int);
|
||||
extern long long _COM_SHLR64 (long long, int);
|
||||
extern long long _COM_SHAR64 (long long, int);
|
||||
extern signed long long _COM_CONVf64s (float);
|
||||
extern unsigned long long _COM_CONVf64u (float);
|
||||
extern signed long long _COM_CONVd64s (double);
|
||||
extern unsigned long long _COM_CONVd64u (double);
|
||||
extern float _COM_CONV64sf (signed long long);
|
||||
extern float _COM_CONV64uf (unsigned long long);
|
||||
extern double _COM_CONV64sd (signed long long);
|
||||
extern double _COM_CONV64ud (unsigned long long);
|
||||
extern signed long long _COM_MOD64s (long long, long long);
|
||||
extern unsigned long long _COM_MOD64u (unsigned long long, unsigned long long);
|
||||
extern int _COM_CMPLT64s (long long, long long);
|
||||
extern int _COM_CMPLT64u (unsigned long long, unsigned long long);
|
||||
extern int _COM_CMPGT64s (long long, long long);
|
||||
extern int _COM_CMPGT64u (unsigned long long, unsigned long long);
|
||||
extern int _COM_CMPLE64s (long long, long long);
|
||||
extern int _COM_CMPLE64u (unsigned long long, unsigned long long);
|
||||
extern int _COM_CMPGE64s (long long, long long);
|
||||
extern int _COM_CMPGE64u (unsigned long long, unsigned long long);
|
||||
extern int _COM_CMPEQ64 (long long, long long);
|
||||
extern int _COM_CMPNE64 (long long, long long);
|
||||
|
||||
extern double _COM_ADDd (double, double);
|
||||
extern double _COM_SUBd (double, double);
|
||||
extern double _COM_MULd (double, double);
|
||||
extern double _COM_DIVd (double, double);
|
||||
extern signed long _COM_CONVd32s (double);
|
||||
extern unsigned long _COM_CONVd32u (double);
|
||||
extern double _COM_CONV32sd (signed long);
|
||||
extern double _COM_CONV32ud (unsigned long);
|
||||
extern double _COM_CONVfd (float);
|
||||
extern float _COM_CONVdf (double);
|
||||
extern double _COM_NEGd (double);
|
||||
|
||||
|
||||
/* #define DEBUG 1 */
|
||||
|
||||
#ifdef DEBUG
|
||||
# define TEST1(func,arg1,result) if (func (arg1) != result) printf ("fail: " #func " (" #arg1 ") returns %x rather than " #result "\n", func (arg1))
|
||||
# define TEST2(func,arg1,arg2,result) if (func (arg1, arg2) != result) printf ("fail: " #func " (" #arg1 ", " #arg2 ") returns %x rather than " #result "\n", func (arg1, arg2))
|
||||
# define TEST_CMP(func, low_arg, high_arg, lt_result, eq_result, gt_result) \
|
||||
do \
|
||||
{ \
|
||||
int res; \
|
||||
\
|
||||
if ((res = func (low_arg, high_arg)) != lt_result) printf ("fail: " #func " (" #low_arg ", " #high_arg ") returns %d rather than %d\n", res, lt_result); \
|
||||
if ((res = func (high_arg, low_arg)) != gt_result) printf ("fail: " #func " (" #high_arg ", " #low_arg ") returns %d rather than %d\n", res, gt_result); \
|
||||
if ((res = func (low_arg, low_arg)) != eq_result) printf ("fail: " #func " (" #low_arg ", " #low_arg ") returns %d rather than %d\n", res, eq_result); \
|
||||
} \
|
||||
while (0)
|
||||
#else
|
||||
# define TEST1(func,arg1,result) if (func (arg1) != result) abort ()
|
||||
# define TEST2(func,arg1,arg2,result) if (func (arg1, arg2) != result) abort ()
|
||||
# define TEST_CMP(func,low,high,lt_res,eq_res,gt_res) \
|
||||
if ( (func (low, high) != lt_res) \
|
||||
|| (func (high, low) != gt_res) \
|
||||
|| (func (low, low) != eq_res)) \
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf ("Tests starting\n");
|
||||
#endif
|
||||
|
||||
TEST1 (_COM_CONVf32s, -2.0f, -2);
|
||||
TEST1 (_COM_CONVf32u, -2.0f, (unsigned) -2);
|
||||
TEST1 (_COM_CONV32sf, -2, -2.0f);
|
||||
TEST1 (_COM_CONV32uf, 2, 2.0f);
|
||||
TEST2 (_COM_ADDf, 1.0f, 2.0f, 3.0f);
|
||||
TEST2 (_COM_SUBf, 3.0f, 2.0f, 1.0f);
|
||||
TEST2 (_COM_MULf, 2.0f, 3.0f, 6.0f);
|
||||
TEST2 (_COM_DIVf, 6.0f, 2.0f, 3.0f);
|
||||
TEST_CMP (_COM_CMPLTf, 1.0f, 2.0f, 1, 0, 0);
|
||||
TEST_CMP (_COM_CMPGTf, 1.0f, 2.0f, 0, 0, 1);
|
||||
TEST_CMP (_COM_CMPLEf, 1.0f, 2.0f, 1, 1, 0);
|
||||
TEST_CMP (_COM_CMPGEf, 1.0f, 2.0f, 0, 1, 1);
|
||||
TEST_CMP (_COM_CMPEQf, 1.0f, 2.0f, 0, 1, 0);
|
||||
TEST_CMP (_COM_CMPNEf, 1.0f, 2.0f, 1, 0, 1);
|
||||
|
||||
|
||||
TEST2 (_COM_MUL64, 2LL, 4LL, 8LL);
|
||||
TEST2 (_COM_DIV64s, 6LL, 3LL, 2LL);
|
||||
TEST2 (_COM_DIV64u, 6ULL, 3ULL, 2ULL);
|
||||
TEST2 (_COM_SHLL64, 6LL, 3, 48LL);
|
||||
TEST2 (_COM_SHLR64, 8LL, 2, 2LL);
|
||||
TEST2 (_COM_SHAR64, -1LL, 2, -1LL);
|
||||
TEST1 (_COM_CONVf64s, -2.0f, -2LL);
|
||||
TEST1 (_COM_CONVf64u, 2.0f, 2ULL);
|
||||
TEST1 (_COM_CONVd64s, -2.0, -2LL);
|
||||
TEST1 (_COM_CONVd64u, 2.0, 2ULL);
|
||||
TEST1 (_COM_CONV64sf, -2LL, -2.0f);
|
||||
TEST1 (_COM_CONV64uf, 2ULL, 2.0f);
|
||||
TEST1 (_COM_CONV64sd, -2LL, -2.0);
|
||||
TEST1 (_COM_CONV64ud, 2ULL, 2.0);
|
||||
TEST2 (_COM_MOD64s, 4LL, 3LL, 1LL);
|
||||
TEST2 (_COM_MOD64u, 4ULL, 3ULL, 1ULL);
|
||||
TEST_CMP (_COM_CMPLT64s, 1LL, 2LL, 1, 0, 0);
|
||||
TEST_CMP (_COM_CMPLT64u, 1ULL, 2ULL, 1, 0, 0);
|
||||
TEST_CMP (_COM_CMPGT64s, 1LL, 2LL, 0, 0, 1);
|
||||
TEST_CMP (_COM_CMPGT64u, 1ULL, 2ULL, 0, 0, 1);
|
||||
TEST_CMP (_COM_CMPLE64s, 1LL, 2LL, 1, 1, 0);
|
||||
TEST_CMP (_COM_CMPLE64u, 1ULL, 2ULL, 1, 1, 0);
|
||||
TEST_CMP (_COM_CMPGE64s, 1LL, 2LL, 0, 1, 1);
|
||||
TEST_CMP (_COM_CMPGE64u, 1ULL, 2ULL, 0, 1, 1);
|
||||
TEST_CMP (_COM_CMPEQ64, 1LL, 2LL, 0, 1, 0);
|
||||
TEST_CMP (_COM_CMPNE64, 1LL, 2LL, 1, 0, 1);
|
||||
|
||||
|
||||
TEST2 (_COM_ADDd, 1.0, 2.0, 3.0);
|
||||
TEST2 (_COM_SUBd, 3.0, 2.0, 1.0);
|
||||
TEST2 (_COM_MULd, 2.0, 3.0, 6.0);
|
||||
TEST2 (_COM_DIVd, 6.0, 2.0, 3.0);
|
||||
TEST1 (_COM_CONVd32s, -2.0, -2);
|
||||
TEST1 (_COM_CONVd32u, -2.0, (unsigned) -2);
|
||||
TEST1 (_COM_CONV32sd, -2, -2.0);
|
||||
TEST1 (_COM_CONV32ud, 2, 2.0);
|
||||
TEST1 (_COM_CONVfd, 2.0f, 2.0);
|
||||
TEST1 (_COM_CONVdf, 2.0, 2.0f);
|
||||
TEST1 (_COM_NEGd, -2.0, 2.0);
|
||||
TEST_CMP (_COM_CMPLTd, 1.0, 2.0, 1, 0, 0);
|
||||
TEST_CMP (_COM_CMPGTd, 1.0, 2.0, 0, 0, 1);
|
||||
TEST_CMP (_COM_CMPLEd, 1.0, 2.0, 1, 1, 0);
|
||||
TEST_CMP (_COM_CMPGEd, 1.0, 2.0, 0, 1, 1);
|
||||
TEST_CMP (_COM_CMPEQd, 1.0, 2.0, 0, 1, 0);
|
||||
TEST_CMP (_COM_CMPNEd, 1.0, 2.0, 1, 0, 1);
|
||||
|
||||
#ifdef DEBUG
|
||||
printf ("Tests finished\n");
|
||||
#endif
|
||||
exit (0);
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# Copyright (C) 2008 Free Software Foundation, Inc.
|
||||
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
# GCC testsuite that uses the `dg.exp' driver.
|
||||
|
||||
# Exit immediately if this isn't the right target.
|
||||
if { ![istarget rx-*-*] } then {
|
||||
return
|
||||
}
|
||||
|
||||
# Load support procs.
|
||||
load_lib gcc-dg.exp
|
||||
|
||||
# If a testcase doesn't have special options, use these.
|
||||
global DEFAULT_CFLAGS
|
||||
if ![info exists DEFAULT_CFLAGS] then {
|
||||
set DEFAULT_CFLAGS ""
|
||||
}
|
||||
|
||||
# Initialize `dg'.
|
||||
dg-init
|
||||
|
||||
# Find all tests
|
||||
set tests [lsort [find $srcdir/$subdir *.\[cS\]]]
|
||||
|
||||
# Main loop.
|
||||
gcc-dg-runtest $tests $DEFAULT_CFLAGS
|
||||
|
||||
# All done.
|
||||
dg-finish
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* { dg-do run { xfail rx-*-* } } */
|
||||
/* { dg-skip-if "skipped until patch for generic zero=width bit-field handling is accepted" { rx-*-* } { "*" } { "" } } */
|
||||
/* { dg-options "-msim" } */
|
||||
/* Note: The -msim abiove is actually there to override the default
|
||||
options which do not allow the GCC extension of zero-width bitfields. */
|
||||
|
||||
extern void abort (void);
|
||||
extern void exit (int);
|
||||
|
||||
struct S_zero
|
||||
{
|
||||
int f1: 4;
|
||||
int f2: 0;
|
||||
short f3: 4;
|
||||
} S_zero;
|
||||
|
||||
struct S_norm
|
||||
{
|
||||
int f1: 4;
|
||||
short f3: 4;
|
||||
} S_norm;
|
||||
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
if (sizeof (S_zero) != 4 || sizeof (S_norm) != 8)
|
||||
abort ();
|
||||
|
||||
exit (0);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -501,6 +501,7 @@ proc check_profiling_available { test_what } {
|
|||
|| [istarget mep-*-elf]
|
||||
|| [istarget mips*-*-elf*]
|
||||
|| [istarget moxie-*-elf*]
|
||||
|| [istarget rx-*-*]
|
||||
|| [istarget xstormy16-*]
|
||||
|| [istarget xtensa*-*-elf]
|
||||
|| [istarget *-*-rtems*]
|
||||
|
|
@ -686,6 +687,18 @@ proc check_effective_target_hard_float { } {
|
|||
}]
|
||||
}
|
||||
|
||||
# This proc is actually checking the availabilty of FPU
|
||||
# support for doubles, so on the RX we must fail if the
|
||||
# 64-bit double multilib has been selected.
|
||||
if { [istarget rx-*-*] } {
|
||||
return 0
|
||||
# return [check_no_compiler_messages hard_float assembly {
|
||||
#if defined __RX_64_BIT_DOUBLES__
|
||||
#error FOO
|
||||
#endif
|
||||
# }]
|
||||
}
|
||||
|
||||
# The generic test equates hard_float with "no call for adding doubles".
|
||||
return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
|
||||
double a (double b, double c) { return b + c; }
|
||||
|
|
@ -2505,8 +2518,8 @@ proc check_effective_target_vect_short_mult { } {
|
|||
if { [istarget ia64-*-*]
|
||||
|| [istarget spu-*-*]
|
||||
|| [istarget i?86-*-*]
|
||||
|| [istarget x86_64-*-*]
|
||||
|| [istarget powerpc*-*-*]
|
||||
|| [istarget x86_64-*-*]
|
||||
|| [istarget powerpc*-*-*]
|
||||
|| [check_effective_target_arm32] } {
|
||||
set et_vect_short_mult_saved 1
|
||||
}
|
||||
|
|
@ -2646,7 +2659,7 @@ proc check_effective_target_section_anchors { } {
|
|||
verbose "check_effective_target_section_anchors: using cached result" 2
|
||||
} else {
|
||||
set et_section_anchors_saved 0
|
||||
if { [istarget powerpc*-*-*]
|
||||
if { [istarget powerpc*-*-*]
|
||||
|| [istarget arm*-*-*] } {
|
||||
set et_section_anchors_saved 1
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,14 @@
|
|||
2009-10-26 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* config.host: Add support for RX target.
|
||||
* config/rx: New directory.
|
||||
* config/rx/rx-abi-functions.c: New file. Supplementary
|
||||
functions for libgcc to support the RX ABI.
|
||||
* config/rx/rx-abi.h: New file. Supplementary header file for
|
||||
libgcc RX ABI functions.
|
||||
* config/rx/t-rx: New file: Makefile fragment for building
|
||||
libgcc for the RX.
|
||||
|
||||
2009-10-09 Uros Bizjak <ubizjak@gmail.com>
|
||||
|
||||
* config/i386/32/sfp-machine.h (__FP_FRAC_SUB_4): Change operand
|
||||
|
|
|
|||
|
|
@ -482,6 +482,10 @@ rs6000-ibm-aix5.1.* | powerpc-ibm-aix5.1.*)
|
|||
;;
|
||||
rs6000-ibm-aix[56789].* | powerpc-ibm-aix[56789].*)
|
||||
;;
|
||||
rx-*-elf)
|
||||
extra_parts="crtbegin.o crtend.o"
|
||||
tmake_file="rx/t-rx"
|
||||
;;
|
||||
s390-*-linux*)
|
||||
tmake_file="${tmake_file} s390/t-crtstuff s390/t-linux s390/32/t-floattodi"
|
||||
;;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,90 @@
|
|||
/* RX C ABI functions
|
||||
Copyright (C) 2009 Free Software Foundation, Inc.
|
||||
Contributed by Red Hat.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
|
||||
/* The RX C ABI includes the specification of a set of compiler support
|
||||
functions. Libgcc2 includes some of them, although the names have to
|
||||
be changed (see rx-abi.h), and the rest are defined here.
|
||||
|
||||
FIXME: Given that FINE_GRAINED_LIBRARIES is defined we ought to consider
|
||||
compiling this file multiple times with one function per iteration being
|
||||
compiled. */
|
||||
|
||||
#ifdef __RX_64BIT_DOUBLES__
|
||||
|
||||
int _COM_CMPLTd (double a, double b) { return __ltdf2 (a, b) == -1; }
|
||||
int _COM_CMPGTd (double a, double b) { return __gtdf2 (a, b) == 1; }
|
||||
int _COM_CMPLEd (double a, double b) { return __ledf2 (a, b) != 1; }
|
||||
int _COM_CMPGEd (double a, double b) { return __gedf2 (a, b) != -1; }
|
||||
int _COM_CMPEQd (double a, double b) { return __eqdf2 (a, b) == 0; }
|
||||
int _COM_CMPNEd (double a, double b) { return __nedf2 (a, b) != 0; }
|
||||
|
||||
int _COM_CMPLTf (double, double) __attribute__ ((weak, alias ("_COM_CMPLTd")));
|
||||
int _COM_CMPGTf (double, double) __attribute__ ((weak, alias ("_COM_CMPGTd")));
|
||||
int _COM_CMPLEf (double, double) __attribute__ ((weak, alias ("_COM_CMPLEd")));
|
||||
int _COM_CMPGEf (double, double) __attribute__ ((weak, alias ("_COM_CMPGEd")));
|
||||
int _COM_CMPEQf (double, double) __attribute__ ((weak, alias ("_COM_CMPEQd")));
|
||||
int _COM_CMPNEf (double, double) __attribute__ ((weak, alias ("_COM_CMPNEd")));
|
||||
|
||||
#else /* 32-bit doubles. */
|
||||
|
||||
double _COM_CONVfd (float a) { return a; }
|
||||
float _COM_CONVdf (double a) { return a; }
|
||||
|
||||
int _COM_CMPLTd (double a, double b) __attribute__ ((weak, alias ("_COM_CMPLTf")));
|
||||
int _COM_CMPGTd (double a, double b) __attribute__ ((weak, alias ("_COM_CMPGTf")));
|
||||
int _COM_CMPLEd (double a, double b) __attribute__ ((weak, alias ("_COM_CMPLEf")));
|
||||
int _COM_CMPGEd (double a, double b) __attribute__ ((weak, alias ("_COM_CMPGEf")));
|
||||
int _COM_CMPEQd (double a, double b) __attribute__ ((weak, alias ("_COM_CMPEQf")));
|
||||
int _COM_CMPNEd (double a, double b) __attribute__ ((weak, alias ("_COM_CMPNEf")));
|
||||
|
||||
signed long long _COM_CONVd64s (double a) { return (signed long long) a; }
|
||||
unsigned long long _COM_CONVd64u (double a) { return (unsigned long long) a; }
|
||||
|
||||
int _COM_CMPLTf (float a, float b) { return __ltsf2 (a, b) == -1; }
|
||||
int _COM_CMPGTf (float a, float b) { return __gtsf2 (a, b) == 1; }
|
||||
int _COM_CMPLEf (float a, float b) { return __lesf2 (a, b) != 1; }
|
||||
int _COM_CMPGEf (float a, float b) { return __gesf2 (a, b) != -1; }
|
||||
int _COM_CMPEQf (float a, float b) { return __eqsf2 (a, b) == 0; }
|
||||
int _COM_CMPNEf (float a, float b) { return __nesf2 (a, b) != 0; }
|
||||
|
||||
#endif /* 64-bit vs 32-bit doubles. */
|
||||
|
||||
double _COM_CONV64sd (signed long long a) { return (double) a; }
|
||||
double _COM_CONV64ud (unsigned long long a) { return (double) a; }
|
||||
|
||||
extern int __cmpdi2 (long long, long long);
|
||||
extern int __ucmpdi2 (long long, long long);
|
||||
|
||||
int _COM_CMPLT64s (long long a, long long b) { return __cmpdi2 (a, b) == 0; }
|
||||
int _COM_CMPLT64u (long long a, long long b) { return __ucmpdi2 (a, b) == 0; }
|
||||
int _COM_CMPGT64s (long long a, long long b) { return __cmpdi2 (a, b) == 2; }
|
||||
int _COM_CMPGT64u (long long a, long long b) { return __ucmpdi2 (a, b) == 2; }
|
||||
int _COM_CMPLE64s (long long a, long long b) { return __cmpdi2 (a, b) != 2; }
|
||||
int _COM_CMPLE64u (long long a, long long b) { return __ucmpdi2 (a, b) != 2; }
|
||||
int _COM_CMPGE64s (long long a, long long b) { return __cmpdi2 (a, b) != 0; }
|
||||
int _COM_CMPGE64u (long long a, long long b) { return __ucmpdi2 (a, b) != 0; }
|
||||
int _COM_CMPEQ64 (long long a, long long b) { return __cmpdi2 (a, b) == 1; }
|
||||
int _COM_CMPNE64 (long long a, long long b) { return __cmpdi2 (a, b) != 1; }
|
||||
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
/* Header file for RX ABI versions of libgcc functions.
|
||||
Copyright (C) 2009
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Red Hat.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Make __COM_<RX_NAME> an alias for __<GCC_NAME>. */
|
||||
#define RENAME_LIBRARY(GCC_NAME, RX_NAME) \
|
||||
__asm__ (".globl\t__COM_" #RX_NAME "\n" \
|
||||
".set\t__COM_" #RX_NAME ", ___" #GCC_NAME "\n");
|
||||
|
||||
|
||||
/* The long-long aliases... */
|
||||
|
||||
#ifdef L_muldi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, MUL64)
|
||||
#endif
|
||||
|
||||
#ifdef L_divdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divdi3, DIV64s)
|
||||
#endif
|
||||
|
||||
#ifdef L_udivdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivdi3, DIV64u)
|
||||
#endif
|
||||
|
||||
#ifdef L_ashldi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashldi3, SHLL64)
|
||||
#endif
|
||||
|
||||
#ifdef L_lshrdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (lshrdi3, SHLR64)
|
||||
#endif
|
||||
|
||||
#ifdef L_ashrdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashrdi3, SHAR64)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixsfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, CONVf64s)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixunssfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, CONVf64u)
|
||||
#endif
|
||||
|
||||
#ifdef L_floatdisf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, CONV64sf)
|
||||
#endif
|
||||
|
||||
#ifdef L_floatundisf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatundisf, CONV64uf)
|
||||
#endif
|
||||
|
||||
#ifdef L_moddi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (moddi3, MOD64s)
|
||||
#endif
|
||||
|
||||
#ifdef L_umoddi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (umoddi3, MOD64u)
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef L_si_to_sf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatsisf, CONV32sf)
|
||||
#endif
|
||||
|
||||
#ifdef L_usi_to_sf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatunsisf, CONV32uf)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef __RX_64BIT_DOUBLES__
|
||||
|
||||
/* Float (32-bit) aliases... */
|
||||
|
||||
#ifdef L_sf_to_si
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfsi, CONVf32s)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixunssfsi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfsi, CONVf32u)
|
||||
#endif
|
||||
|
||||
#ifdef L_addsub_sf
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (addsf3, ADDf) \
|
||||
RENAME_LIBRARY (subsf3, SUBf)
|
||||
#endif
|
||||
|
||||
#ifdef L_mul_sf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (mulsf3, MULf)
|
||||
#endif
|
||||
|
||||
#ifdef L_div_sf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divsf3, DIVf)
|
||||
#endif
|
||||
|
||||
/* Double (64-bit) aliases... */
|
||||
|
||||
#ifdef L_addsub_df
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (adddf3, ADDd) \
|
||||
RENAME_LIBRARY (subdf3, SUBd)
|
||||
#endif
|
||||
|
||||
#ifdef L_mul_df
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldf3, MULd)
|
||||
#endif
|
||||
|
||||
#ifdef L_div_df
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divdf3, DIVd)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixdfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, CONVd64s)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixunsdfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, CONVd64u)
|
||||
#endif
|
||||
|
||||
#ifdef L_floatdidf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, CONV64sd)
|
||||
#endif
|
||||
|
||||
#ifdef L_floatundidf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, CONV64ud)
|
||||
#endif
|
||||
|
||||
#ifdef L_df_to_si
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfsi, CONVd32s)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixunsdfsi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfsi, CONVd32u)
|
||||
#endif
|
||||
|
||||
#ifdef L_si_to_df
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatsidf, CONV32sd)
|
||||
#endif
|
||||
|
||||
#ifdef L_usi_to_df
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatunsidf, CONV32ud)
|
||||
#endif
|
||||
|
||||
#ifdef L_sf_to_df
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (extendsfdf2, CONVfd)
|
||||
#endif
|
||||
|
||||
#ifdef L_df_to_sf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (truncdfsf2, CONVdf)
|
||||
#endif
|
||||
|
||||
#ifdef L_negate_df
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (negdf2, NEGd)
|
||||
#endif
|
||||
|
||||
/* The 64-bit comparison functions do not have aliases because libgcc2
|
||||
does not provide them. Instead they have to be supplied in
|
||||
rx-abi-functions.c. */
|
||||
|
||||
|
||||
#else /* 32-bit doubles. */
|
||||
|
||||
|
||||
#ifdef L_addsub_sf
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (addsf3, ADDd) \
|
||||
RENAME_LIBRARY (subsf3, SUBd) \
|
||||
RENAME_LIBRARY (addsf3, ADDf) \
|
||||
RENAME_LIBRARY (subsf3, SUBf)
|
||||
#endif
|
||||
|
||||
#ifdef L_mul_sf
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (mulsf3, MULd) \
|
||||
RENAME_LIBRARY (mulsf3, MULf)
|
||||
#endif
|
||||
|
||||
#ifdef L_div_sf
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (divsf3, DIVd) \
|
||||
RENAME_LIBRARY (divsf3, DIVf)
|
||||
#endif
|
||||
|
||||
#ifdef L_sf_to_si
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (fixsfsi, CONVd32s) \
|
||||
RENAME_LIBRARY (fixsfsi, CONVf32s)
|
||||
#endif
|
||||
|
||||
#ifdef L_fixunssfsi
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (fixunssfsi, CONVd32u) \
|
||||
RENAME_LIBRARY (fixunssfsi, CONVf32u)
|
||||
#endif
|
||||
|
||||
#ifdef L_si_to_sf
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (floatsisf, CONV32sd) \
|
||||
RENAME_LIBRARY (floatsisf, CONV32sf)
|
||||
#endif
|
||||
|
||||
#ifdef L_usi_to_sf
|
||||
#define DECLARE_LIBRARY_RENAMES \
|
||||
RENAME_LIBRARY (floatunsisf, CONV32ud) \
|
||||
RENAME_LIBRARY (floatunsisf, CONV32uf)
|
||||
#endif
|
||||
|
||||
#ifdef L_negate_sf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (negsf2, NEGd)
|
||||
#endif
|
||||
|
||||
#endif /* 64-bit vs 32-bit doubles. */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# Makefile fragment for building LIBGCC for the Renesas RX target.
|
||||
# Copyright (C) 2008, 2009 Free Software Foundation, Inc.
|
||||
# Contributed by Red Hat.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published
|
||||
# by the Free Software Foundation; either version 3, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful, but
|
||||
# WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
# the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public
|
||||
# License along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
|
||||
# Add functions required by the RX ABI which are not part of
|
||||
# the normal libgcc sources:
|
||||
|
||||
LIB2ADD = $(srcdir)/config/rx/rx-abi-functions.c
|
||||
|
||||
|
||||
# We need special handling of the floating point conversion
|
||||
# routines, to allow for the varying size of a double:
|
||||
|
||||
FPBIT = fp-bit.c
|
||||
$(gcc_objdir)/fp-bit.c: $(gcc_srcdir)/config/fp-bit.c
|
||||
echo '#define FLOAT' > $@
|
||||
echo '#ifndef __RX_64BIT_DOUBLES__' >> $@
|
||||
echo '#define DF SF' >> $@
|
||||
echo '#define FLOAT_ONLY' >> $@
|
||||
echo '#endif' >> $@
|
||||
cat $(gcc_srcdir)/config/fp-bit.c >> $@
|
||||
|
||||
DPBIT = dp-bit.c
|
||||
$(gcc_objdir)/dp-bit.c: $(gcc_srcdir)/config/fp-bit.c
|
||||
echo '#ifdef __RX_64BIT_DOUBLES__' > $@
|
||||
cat $(gcc_srcdir)/config/fp-bit.c >> $@
|
||||
echo '#endif' >> $@
|
||||
Loading…
Reference in New Issue