aarch64: Stop +mops clobbering variable values
The mops cpy* patterns take three registers: a destination address,
a source address, and a size. The patterns clobber all three registers
as part of the operation. The set* patterns take a destination address,
a size, and a store value, and they clobber the first two registers as
part of the operation.
However, the associated expanders would try to use existing source,
destination and size registers where possible. Any variables in
those registers could therefore change unexpectedly.
For example:
void
copy1 (int *x, int *y, long z, int **res)
{
__builtin_memcpy (x, y, z);
*res = x;
}
generated:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
str x0, [x3]
ret
which stores the incremented x at *res.
gcc/
* config/aarch64/aarch64.md (aarch64_cpymemdi): Turn into a
define_expand and turn operands 0 and 1 from REGs to MEMs.
(*aarch64_cpymemdi): New pattern.
(aarch64_setmemdi): Turn into a define_expand and turn operand 0
from a REG to a MEM.
(*aarch64_setmemdi): New pattern.
* config/aarch64/aarch64.cc (aarch64_expand_cpymem_mops): Use
copy_to_mode_reg on all three registers. Replace the original
MEM addresses rather than creating wild reads and writes.
(aarch64_expand_setmem_mops): Likewise for the size and for the
destination memory and address.
gcc/testsuite/
* gcc.target/aarch64/mops_4.c: New test.
This commit is contained in:
Richard Sandiford
parent
14814e2016
commit
65b77d0eec
@ -24531,17 +24531,15 @@ aarch64_expand_cpymem_mops (rtx *operands)
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{
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if (!TARGET_MOPS)
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return false;
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rtx addr_dst = XEXP (operands[0], 0);
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rtx addr_src = XEXP (operands[1], 0);
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rtx sz_reg = operands[2];
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if (!REG_P (sz_reg))
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sz_reg = force_reg (DImode, sz_reg);
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if (!REG_P (addr_dst))
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addr_dst = force_reg (DImode, addr_dst);
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if (!REG_P (addr_src))
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addr_src = force_reg (DImode, addr_src);
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emit_insn (gen_aarch64_cpymemdi (addr_dst, addr_src, sz_reg));
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/* All three registers are changed by the instruction, so each one
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must be a fresh pseudo. */
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rtx dst_addr = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
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rtx src_addr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
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rtx dst_mem = replace_equiv_address (operands[0], dst_addr);
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rtx src_mem = replace_equiv_address (operands[1], src_addr);
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rtx sz_reg = copy_to_mode_reg (DImode, operands[2]);
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emit_insn (gen_aarch64_cpymemdi (dst_mem, src_mem, sz_reg));
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return true;
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}
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@ -24718,17 +24716,15 @@ aarch64_expand_setmem_mops (rtx *operands)
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if (!TARGET_MOPS)
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return false;
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rtx addr_dst = XEXP (operands[0], 0);
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rtx sz_reg = operands[1];
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/* The first two registers are changed by the instruction, so both
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of them must be a fresh pseudo. */
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rtx dst_addr = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
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rtx dst_mem = replace_equiv_address (operands[0], dst_addr);
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rtx sz_reg = copy_to_mode_reg (DImode, operands[1]);
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rtx val = operands[2];
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if (!REG_P (sz_reg))
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sz_reg = force_reg (DImode, sz_reg);
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if (!REG_P (addr_dst))
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addr_dst = force_reg (DImode, addr_dst);
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if (!REG_P (val) && val != CONST0_RTX (QImode))
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val = force_reg (QImode, val);
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emit_insn (gen_aarch64_setmemdi (addr_dst, val, sz_reg));
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if (val != CONST0_RTX (QImode))
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val = force_reg (QImode, val);
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emit_insn (gen_aarch64_setmemdi (dst_mem, val, sz_reg));
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return true;
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}
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@ -1581,16 +1581,29 @@
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}
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)
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(define_insn "aarch64_cpymemdi"
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[(parallel [
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(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
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(define_expand "aarch64_cpymemdi"
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[(parallel
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[(set (match_operand 2) (const_int 0))
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(clobber (match_dup 3))
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(clobber (match_dup 4))
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(set (match_operand 0)
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(unspec:BLK [(match_operand 1) (match_dup 2)] UNSPEC_CPYMEM))])]
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"TARGET_MOPS"
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{
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operands[3] = XEXP (operands[0], 0);
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operands[4] = XEXP (operands[1], 0);
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}
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)
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(define_insn "*aarch64_cpymemdi"
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[(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
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(clobber (match_operand:DI 0 "register_operand" "+&r"))
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(clobber (match_operand:DI 1 "register_operand" "+&r"))
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(set (mem:BLK (match_dup 0))
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(unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_CPYMEM))])]
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"TARGET_MOPS"
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"cpyfp\t[%x0]!, [%x1]!, %x2!\;cpyfm\t[%x0]!, [%x1]!, %x2!\;cpyfe\t[%x0]!, [%x1]!, %x2!"
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[(set_attr "length" "12")]
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(unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_CPYMEM))]
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"TARGET_MOPS"
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"cpyfp\t[%x0]!, [%x1]!, %x2!\;cpyfm\t[%x0]!, [%x1]!, %x2!\;cpyfe\t[%x0]!, [%x1]!, %x2!"
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[(set_attr "length" "12")]
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)
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;; 0 is dst
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@ -1657,16 +1670,28 @@
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}
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)
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(define_insn "aarch64_setmemdi"
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[(parallel [
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(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
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(define_expand "aarch64_setmemdi"
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[(parallel
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[(set (match_operand 2) (const_int 0))
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(clobber (match_dup 3))
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(set (match_operand 0)
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(unspec:BLK [(match_operand 1)
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(match_dup 2)] UNSPEC_SETMEM))])]
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"TARGET_MOPS"
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{
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operands[3] = XEXP (operands[0], 0);
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}
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)
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(define_insn "*aarch64_setmemdi"
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[(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
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(clobber (match_operand:DI 0 "register_operand" "+&r"))
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(set (mem:BLK (match_dup 0))
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(unspec:BLK [(match_operand:QI 1 "aarch64_reg_or_zero" "rZ")
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(match_dup 2)] UNSPEC_SETMEM))])]
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"TARGET_MOPS"
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"setp\t[%x0]!, %x2!, %x1\;setm\t[%x0]!, %x2!, %x1\;sete\t[%x0]!, %x2!, %x1"
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[(set_attr "length" "12")]
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(match_dup 2)] UNSPEC_SETMEM))]
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"TARGET_MOPS"
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"setp\t[%x0]!, %x2!, %x1\;setm\t[%x0]!, %x2!, %x1\;sete\t[%x0]!, %x2!, %x1"
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[(set_attr "length" "12")]
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)
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;; 0 is dst
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115
gcc/testsuite/gcc.target/aarch64/mops_4.c
Normal file
115
gcc/testsuite/gcc.target/aarch64/mops_4.c
Normal file
@ -0,0 +1,115 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=armv8.6-a+mops" } */
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/* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
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/*
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** copy1:
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** mov (x[0-9]+), x0
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** cpyfp \[\1\]!, \[x1\]!, x2!
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** cpyfm \[\1\]!, \[x1\]!, x2!
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** cpyfe \[\1\]!, \[x1\]!, x2!
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** str x0, \[x3\]
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** ret
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*/
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void
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copy1 (int *x, int *y, long z, int **res)
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{
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__builtin_memcpy (x, y, z);
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*res = x;
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}
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/*
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** copy2:
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** mov (x[0-9]+), x1
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** cpyfp \[x0\]!, \[\1\]!, x2!
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** cpyfm \[x0\]!, \[\1\]!, x2!
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** cpyfe \[x0\]!, \[\1\]!, x2!
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** str x1, \[x3\]
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** ret
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*/
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void
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copy2 (int *x, int *y, long z, int **res)
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{
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__builtin_memcpy (x, y, z);
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*res = y;
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}
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/*
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** copy3:
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** mov (x[0-9]+), x2
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** cpyfp \[x0\]!, \[x1\]!, \1!
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** cpyfm \[x0\]!, \[x1\]!, \1!
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** cpyfe \[x0\]!, \[x1\]!, \1!
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** str x2, \[x3\]
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** ret
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*/
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void
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copy3 (int *x, int *y, long z, long *res)
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{
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__builtin_memcpy (x, y, z);
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*res = z;
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}
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/*
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** set1:
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** mov (x[0-9]+), x0
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** setp \[\1\]!, x2!, x1
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** setm \[\1\]!, x2!, x1
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** sete \[\1\]!, x2!, x1
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** str x0, \[x3\]
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** ret
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*/
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void
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set1 (char *x, char y, long z, char **res)
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{
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__builtin_memset (x, y, z);
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*res = x;
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}
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/*
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** set2:
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** ldrb w([0-9]+), \[x1\]
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** setp \[x0\]!, x2!, x\1
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** setm \[x0\]!, x2!, x\1
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** sete \[x0\]!, x2!, x\1
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** strb w\1, \[x3\]
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** ret
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*/
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void
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set2 (char *x, char *yptr, long z, char *res)
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{
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char y = *yptr;
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__builtin_memset (x, y, z);
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*res = y;
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}
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/*
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** set3:
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** mov (x[0-9]+), x2
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** setp \[x0\]!, \1!, x1
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** setm \[x0\]!, \1!, x1
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** sete \[x0\]!, \1!, x1
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** str x2, \[x3\]
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** ret
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*/
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void
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set3 (char *x, char y, long z, long *res)
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{
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__builtin_memset (x, y, z);
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*res = z;
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}
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/*
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** set4:
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** setp \[x0\]!, x1!, xzr
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** setm \[x0\]!, x1!, xzr
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** sete \[x0\]!, x1!, xzr
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** strb wzr, \[x2\]
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** ret
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*/
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void
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set4 (char *x, long z, char *res)
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{
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__builtin_memset (x, 0, z);
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*res = 0;
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}
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