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Fix ICE on empty FIQ interrupt handler on ARM 

2016-11-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.md (arm_addsi3): Add alternative for addition of
    general register with general register or ARM constant into SP
    register.

    gcc/testsuite/
    * gcc.target/arm/empty_fiq_handler.c: New test.

From-SVN: r242508
This commit is contained in:
Thomas Preud'homme 2016-11-16 18:30:56 +00:00 committed by Thomas Preud'homme
parent 5e8d7713be
commit 660e6c2c12
4 changed files with 28 additions and 6 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2016-11-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm.md (arm_addsi3): Add alternative for addition of
general register with general register or ARM constant into SP
register.
2016-11-16 Jakub Jelinek <jakub@redhat.com>
PR fortran/78299

13
gcc/config/arm/arm.md
View File

@ -609,9 +609,9 @@
;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
;; put the duplicated register first, and not try the commutative version.
(define_insn_and_split "*arm_addsi3"
[(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r")
(plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk")
(match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
[(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r")
(plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk")
(match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
"TARGET_32BIT"
"@
add%?\\t%0, %0, %2
@ -621,6 +621,7 @@
add%?\\t%0, %1, %2
add%?\\t%0, %1, %2
add%?\\t%0, %2, %1
add%?\\t%0, %1, %2
addw%?\\t%0, %1, %2
addw%?\\t%0, %1, %2
sub%?\\t%0, %1, #%n2
@ -640,10 +641,10 @@
operands[1], 0);
DONE;
"
[(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
[(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_imm")
(const_string "alu_sreg")))

4
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2016-11-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
* gcc.target/arm/empty_fiq_handler.c: New test.
2016-11-16 Jakub Jelinek <jakub@redhat.com>
PR fortran/78299

11
gcc/testsuite/gcc.target/arm/empty_fiq_handler.c Normal file
View File

@ -0,0 +1,11 @@
/* { dg-do compile } */
/* Below code used to trigger an ICE due to missing constraints for
sp = fp + cst pattern. */
void fiq_handler (void) __attribute__((interrupt ("FIQ")));
void
fiq_handler (void)
{
}