OpenE2K
/
gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

aix.h (OS_MISSING_POWERPC64): Define. 

* config/rs6000/aix.h (OS_MISSING_POWERPC64): Define.
	(OS_MISSING_ALTIVEC): Define.
	* config/rs6000/darwin.h (ASM_SPEC): Be generous about supplying
	-force_cpusubtype_ALL.
	* config/rs6000/rs6000.c (rs6000_override_options): Rearrange
	CPU information table; now always set all CPU-specific values.
	Also, use Altivec and powerpc64 when chip and OS supports them.

From-SVN: r74820
This commit is contained in:
Geoffrey Keating 2003-12-19 06:28:24 +00:00 committed by Geoffrey Keating
parent 3afbff37c4
commit 66188a7ef3
5 changed files with 131 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2003-12-18 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/aix.h (OS_MISSING_POWERPC64): Define.
(OS_MISSING_ALTIVEC): Define.
* config/rs6000/darwin.h (ASM_SPEC): Be generous about supplying
-force_cpusubtype_ALL.
* config/rs6000/rs6000.c (rs6000_override_options): Rearrange
CPU information table; now always set all CPU-specific values.
Also, use Altivec and powerpc64 when chip and OS supports them.
2003-12-18 Geoffrey Keating <geoffk@apple.com>
* fixinc/inclhack.def (darwin_macho_dyldh): New.

5
gcc/config/rs6000/aix.h
View File

@ -241,3 +241,8 @@
/* Print subsidiary information on the compiler version in use. */
#define TARGET_VERSION ;
/* No version of AIX fully supports AltiVec or 64-bit instructions in
32-bit mode. */
#define OS_MISSING_POWERPC64 1
#define OS_MISSING_ALTIVEC 1

7
gcc/config/rs6000/darwin.h
View File

@ -98,9 +98,14 @@ do { \
%{static: %{Zdynamic: %e conflicting code gen style switches are used}}\
%{!static:%{!mdynamic-no-pic:-fPIC}}"
/* It's virtually impossible to predict all the possible combinations
of -mcpu and -maltivec and whatnot, so just supply
-force_cpusubtype_ALL if any are seen. Radar 3492132 against the
assembler is asking for a .machine directive so we could get this
really right. */
#define ASM_SPEC "-arch ppc \
%{Zforce_cpusubtype_ALL:-force_cpusubtype_ALL} \
%{!Zforce_cpusubtype_ALL:%{maltivec:-force_cpusubtype_ALL}}"
%{!Zforce_cpusubtype_ALL:%{maltivec|mcpu=*|mpowerpc64:-force_cpusubtype_ALL}}"
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \

215
gcc/config/rs6000/rs6000.c
View File

@ -624,147 +624,79 @@ rs6000_override_options (const char *default_cpu)
{
size_t i, j;
struct rs6000_cpu_select *ptr;
int set_masks;
/* Simplify the entries below by making a mask for any POWER
variant and any PowerPC variant. */
/* Simplifications for entries below. */
#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
| MASK_PPC_GFXOPT | MASK_POWERPC64)
#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
enum {
POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
};
/* This table occasionally claims that a processor does not support
a particular feature even though it does, but the feature is slower
than the alternative. Thus, it shouldn't be relied on as a
complete description of the processor's support.
Please keep this list in order, and don't forget to update the
documentation in invoke.texi when adding a new processor or
flag. */
static struct ptt
{
const char *const name; /* Canonical processor name. */
const enum processor_type processor; /* Processor type enum value. */
const int target_enable; /* Target flags to enable. */
const int target_disable; /* Target flags to disable. */
} const processor_target_table[]
= {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_MASKS},
{"power", PROCESSOR_POWER,
MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"power2", PROCESSOR_POWER,
MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"power3", PROCESSOR_PPC630,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS},
{"power4", PROCESSOR_POWER4,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS | MASK_MFCRF,
POWER_MASKS},
{"powerpc", PROCESSOR_POWERPC,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"powerpc64", PROCESSOR_POWERPC64,
MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS},
{"rios", PROCESSOR_RIOS1,
MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rios1", PROCESSOR_RIOS1,
MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rsc", PROCESSOR_PPC601,
MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rsc1", PROCESSOR_PPC601,
MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rs64a", PROCESSOR_RS64A,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS},
{"401", PROCESSOR_PPC403,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
= {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"403", PROCESSOR_PPC403,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"405", PROCESSOR_PPC405,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"405fp", PROCESSOR_PPC405,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"440", PROCESSOR_PPC440,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"440fp", PROCESSOR_PPC440,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"505", PROCESSOR_MPCCORE,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
{"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
{"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
{"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
{"601", PROCESSOR_PPC601,
MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"602", PROCESSOR_PPC603,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"603", PROCESSOR_PPC603,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"603e", PROCESSOR_PPC603,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"ec603e", PROCESSOR_PPC603,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"604", PROCESSOR_PPC604,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"604e", PROCESSOR_PPC604e,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"620", PROCESSOR_PPC620,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS},
{"630", PROCESSOR_PPC630,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS},
{"740", PROCESSOR_PPC750,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"750", PROCESSOR_PPC750,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"G3", PROCESSOR_PPC750,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"7400", PROCESSOR_PPC7400,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"7450", PROCESSOR_PPC7450,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"G4", PROCESSOR_PPC7450,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"8540", PROCESSOR_PPC8540,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"801", PROCESSOR_MPCCORE,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"821", PROCESSOR_MPCCORE,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"823", PROCESSOR_MPCCORE,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"860", PROCESSOR_MPCCORE,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
{"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"620", PROCESSOR_PPC620, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"630", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
{"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
{"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"970", PROCESSOR_POWER4,
MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
POWER_MASKS},
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
{"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
{"G5", PROCESSOR_POWER4,
MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
POWER_MASKS}};
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
{"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"power2", PROCESSOR_POWER,
MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
{"power3", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"power4", PROCESSOR_POWER4, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
POWERPC_BASE_MASK | MASK_POWERPC64},
{"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
{"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK},
};
const size_t ptt_size = ARRAY_SIZE (processor_target_table);
@ -773,6 +705,28 @@ rs6000_override_options (const char *default_cpu)
/* Save current -mstring/-mno-string status. */
int string = TARGET_STRING;
/* Some OSs don't support saving the high part of 64-bit registers on
context switch. Other OSs don't support saving Altivec registers.
On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
settings; if the user wants either, the user must explicitly specify
them and we won't interfere with the user's specification. */
enum {
POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
| MASK_MFCRF)
};
set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
#ifdef OS_MISSING_POWERPC64
if (OS_MISSING_POWERPC64)
set_masks &= ~MASK_POWERPC64;
#endif
#ifdef OS_MISSING_ALTIVEC
if (OS_MISSING_ALTIVEC)
set_masks &= ~MASK_ALTIVEC;
#endif
/* Identify the processor type. */
rs6000_select[0].string = default_cpu;
rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
@ -790,8 +744,9 @@ rs6000_override_options (const char *default_cpu)
if (ptr->set_arch_p)
{
target_flags |= processor_target_table[j].target_enable;
target_flags &= ~processor_target_table[j].target_disable;
target_flags &= ~set_masks;
target_flags |= (processor_target_table[j].target_enable
& set_masks);
}
break;
}

72
gcc/doc/invoke.texi
View File

@ -7239,13 +7239,15 @@ should normally not specify either @option{-mnew-mnemonics} or
@opindex mcpu
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type @var{cpu_type}.
Supported values for @var{cpu_type} are @samp{rios}, @samp{rios1},
@samp{rsc}, @samp{rios2}, @samp{rs64a}, @samp{601}, @samp{602},
@samp{603}, @samp{603e}, @samp{604}, @samp{604e}, @samp{620},
@samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{G4},
@samp{750}, @samp{G3}, @samp{power}, @samp{power2}, @samp{powerpc},
@samp{403}, @samp{505}, @samp{801}, @samp{821}, @samp{823}, @samp{860},
@samp{970}, @samp{G5} and @samp{common}.
Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
@samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
@samp{power4}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
@option{-mcpu=common} selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.
@ -7263,47 +7265,23 @@ The other options specify a specific processor. Code generated under
those options will run best on that processor, and may not run at all on
others.
The @option{-mcpu} options automatically enable or disable other
@option{-m} options as follows:
The @option{-mcpu} options automatically enable or disable the
following options: @option{-maltivec}, @option{-mhard-float},
@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
@option{-mstring}. The particular options set for any particular CPU
will vary between compiler versions, depending on what setting seems
to produce optimal code for that CPU; it doesn't necessarily reflect
the actual hardware's capabilities. If you wish to set an individual
option to a particular value, you may specify it after the
@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
@table @samp
@item common
@option{-mno-power}, @option{-mno-powerpc}
@item power
@itemx power2
@itemx rios1
@itemx rios2
@itemx rsc
@option{-mpower}, @option{-mno-powerpc}, @option{-mno-new-mnemonics}
@item powerpc
@itemx rs64a
@itemx 602
@itemx 603
@itemx 603e
@itemx 604
@itemx 620
@itemx 630
@itemx 740
@itemx 7400
@itemx 7450
@itemx G4
@itemx 750
@itemx G3
@itemx 505
@itemx 970
@itemx G5
@option{-mno-power}, @option{-mpowerpc}, @option{-mnew-mnemonics}
@item 601
@option{-mpower}, @option{-mpowerpc}, @option{-mnew-mnemonics}
@item 403
@itemx 821
@itemx 860
@option{-mno-power}, @option{-mpowerpc}, @option{-mnew-mnemonics}, @option{-msoft-float}
@end table
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
not enabled or disabled by the @option{-mcpu} option at present, since
AIX does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
@item -mtune=@var{cpu_type}
@opindex mtune