aix.h (OS_MISSING_POWERPC64): Define.
* config/rs6000/aix.h (OS_MISSING_POWERPC64): Define. (OS_MISSING_ALTIVEC): Define. * config/rs6000/darwin.h (ASM_SPEC): Be generous about supplying -force_cpusubtype_ALL. * config/rs6000/rs6000.c (rs6000_override_options): Rearrange CPU information table; now always set all CPU-specific values. Also, use Altivec and powerpc64 when chip and OS supports them. From-SVN: r74820
This commit is contained in:
parent
3afbff37c4
commit
66188a7ef3
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@ -1,3 +1,13 @@
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2003-12-18 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/aix.h (OS_MISSING_POWERPC64): Define.
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(OS_MISSING_ALTIVEC): Define.
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* config/rs6000/darwin.h (ASM_SPEC): Be generous about supplying
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-force_cpusubtype_ALL.
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* config/rs6000/rs6000.c (rs6000_override_options): Rearrange
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CPU information table; now always set all CPU-specific values.
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Also, use Altivec and powerpc64 when chip and OS supports them.
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2003-12-18 Geoffrey Keating <geoffk@apple.com>
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* fixinc/inclhack.def (darwin_macho_dyldh): New.
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@ -241,3 +241,8 @@
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/* Print subsidiary information on the compiler version in use. */
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#define TARGET_VERSION ;
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/* No version of AIX fully supports AltiVec or 64-bit instructions in
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32-bit mode. */
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#define OS_MISSING_POWERPC64 1
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#define OS_MISSING_ALTIVEC 1
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@ -98,9 +98,14 @@ do { \
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%{static: %{Zdynamic: %e conflicting code gen style switches are used}}\
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%{!static:%{!mdynamic-no-pic:-fPIC}}"
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/* It's virtually impossible to predict all the possible combinations
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of -mcpu and -maltivec and whatnot, so just supply
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-force_cpusubtype_ALL if any are seen. Radar 3492132 against the
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assembler is asking for a .machine directive so we could get this
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really right. */
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#define ASM_SPEC "-arch ppc \
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%{Zforce_cpusubtype_ALL:-force_cpusubtype_ALL} \
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%{!Zforce_cpusubtype_ALL:%{maltivec:-force_cpusubtype_ALL}}"
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%{!Zforce_cpusubtype_ALL:%{maltivec|mcpu=*|mpowerpc64:-force_cpusubtype_ALL}}"
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#undef SUBTARGET_EXTRA_SPECS
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#define SUBTARGET_EXTRA_SPECS \
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@ -624,147 +624,79 @@ rs6000_override_options (const char *default_cpu)
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{
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size_t i, j;
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struct rs6000_cpu_select *ptr;
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int set_masks;
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/* Simplify the entries below by making a mask for any POWER
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variant and any PowerPC variant. */
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/* Simplifications for entries below. */
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#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
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#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
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| MASK_PPC_GFXOPT | MASK_POWERPC64)
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#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
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enum {
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POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
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POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
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};
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/* This table occasionally claims that a processor does not support
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a particular feature even though it does, but the feature is slower
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than the alternative. Thus, it shouldn't be relied on as a
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complete description of the processor's support.
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Please keep this list in order, and don't forget to update the
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documentation in invoke.texi when adding a new processor or
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flag. */
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static struct ptt
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{
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const char *const name; /* Canonical processor name. */
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const enum processor_type processor; /* Processor type enum value. */
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const int target_enable; /* Target flags to enable. */
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const int target_disable; /* Target flags to disable. */
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} const processor_target_table[]
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= {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_MASKS},
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{"power", PROCESSOR_POWER,
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MASK_POWER | MASK_MULTIPLE | MASK_STRING,
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MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"power2", PROCESSOR_POWER,
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MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
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POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"power3", PROCESSOR_PPC630,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS},
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{"power4", PROCESSOR_POWER4,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS | MASK_MFCRF,
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POWER_MASKS},
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{"powerpc", PROCESSOR_POWERPC,
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MASK_POWERPC | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"powerpc64", PROCESSOR_POWERPC64,
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MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS},
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{"rios", PROCESSOR_RIOS1,
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MASK_POWER | MASK_MULTIPLE | MASK_STRING,
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MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"rios1", PROCESSOR_RIOS1,
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MASK_POWER | MASK_MULTIPLE | MASK_STRING,
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MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"rsc", PROCESSOR_PPC601,
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MASK_POWER | MASK_MULTIPLE | MASK_STRING,
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MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"rsc1", PROCESSOR_PPC601,
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MASK_POWER | MASK_MULTIPLE | MASK_STRING,
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MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"rios2", PROCESSOR_RIOS2,
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MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
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POWERPC_MASKS | MASK_NEW_MNEMONICS},
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{"rs64a", PROCESSOR_RS64A,
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MASK_POWERPC | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS},
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{"401", PROCESSOR_PPC403,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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= {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"403", PROCESSOR_PPC403,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"405", PROCESSOR_PPC405,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"405fp", PROCESSOR_PPC405,
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MASK_POWERPC | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"440", PROCESSOR_PPC440,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"440fp", PROCESSOR_PPC440,
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MASK_POWERPC | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"505", PROCESSOR_MPCCORE,
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MASK_POWERPC | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
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{"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
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{"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
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{"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
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{"601", PROCESSOR_PPC601,
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MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
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MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"602", PROCESSOR_PPC603,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"603", PROCESSOR_PPC603,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"603e", PROCESSOR_PPC603,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"ec603e", PROCESSOR_PPC603,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"604", PROCESSOR_PPC604,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"604e", PROCESSOR_PPC604e,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"620", PROCESSOR_PPC620,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS},
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{"630", PROCESSOR_PPC630,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS},
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{"740", PROCESSOR_PPC750,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"750", PROCESSOR_PPC750,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"G3", PROCESSOR_PPC750,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"7400", PROCESSOR_PPC7400,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"7450", PROCESSOR_PPC7450,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"G4", PROCESSOR_PPC7450,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"8540", PROCESSOR_PPC8540,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
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{"801", PROCESSOR_MPCCORE,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"821", PROCESSOR_MPCCORE,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"823", PROCESSOR_MPCCORE,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"860", PROCESSOR_MPCCORE,
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
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{"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"620", PROCESSOR_PPC620, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"630", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
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{"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
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{"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"970", PROCESSOR_POWER4,
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MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
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POWER_MASKS},
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POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
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{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
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{"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
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{"G5", PROCESSOR_POWER4,
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MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
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POWER_MASKS}};
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POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
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{"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
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{"power2", PROCESSOR_POWER,
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MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
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{"power3", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"power4", PROCESSOR_POWER4, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
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{"powerpc64", PROCESSOR_POWERPC64,
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POWERPC_BASE_MASK | MASK_POWERPC64},
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{"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
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{"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
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{"rios2", PROCESSOR_RIOS2,
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MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
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{"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
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{"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
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{"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK},
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};
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const size_t ptt_size = ARRAY_SIZE (processor_target_table);
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|
@ -773,6 +705,28 @@ rs6000_override_options (const char *default_cpu)
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/* Save current -mstring/-mno-string status. */
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int string = TARGET_STRING;
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/* Some OSs don't support saving the high part of 64-bit registers on
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context switch. Other OSs don't support saving Altivec registers.
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On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
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settings; if the user wants either, the user must explicitly specify
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them and we won't interfere with the user's specification. */
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enum {
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POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
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POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
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| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
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| MASK_MFCRF)
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};
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set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
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#ifdef OS_MISSING_POWERPC64
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if (OS_MISSING_POWERPC64)
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set_masks &= ~MASK_POWERPC64;
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#endif
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#ifdef OS_MISSING_ALTIVEC
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if (OS_MISSING_ALTIVEC)
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set_masks &= ~MASK_ALTIVEC;
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#endif
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|
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/* Identify the processor type. */
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rs6000_select[0].string = default_cpu;
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rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
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|
@ -790,8 +744,9 @@ rs6000_override_options (const char *default_cpu)
|
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|
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if (ptr->set_arch_p)
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{
|
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target_flags |= processor_target_table[j].target_enable;
|
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target_flags &= ~processor_target_table[j].target_disable;
|
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target_flags &= ~set_masks;
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target_flags |= (processor_target_table[j].target_enable
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& set_masks);
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}
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break;
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}
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|
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@ -7239,13 +7239,15 @@ should normally not specify either @option{-mnew-mnemonics} or
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@opindex mcpu
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Set architecture type, register usage, choice of mnemonics, and
|
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instruction scheduling parameters for machine type @var{cpu_type}.
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Supported values for @var{cpu_type} are @samp{rios}, @samp{rios1},
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@samp{rsc}, @samp{rios2}, @samp{rs64a}, @samp{601}, @samp{602},
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@samp{603}, @samp{603e}, @samp{604}, @samp{604e}, @samp{620},
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@samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{G4},
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@samp{750}, @samp{G3}, @samp{power}, @samp{power2}, @samp{powerpc},
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@samp{403}, @samp{505}, @samp{801}, @samp{821}, @samp{823}, @samp{860},
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@samp{970}, @samp{G5} and @samp{common}.
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Supported values for @var{cpu_type} are @samp{401}, @samp{403},
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@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
|
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@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
|
||||
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
|
||||
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
|
||||
@samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3},
|
||||
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
|
||||
@samp{power4}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
|
||||
@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
|
||||
|
||||
@option{-mcpu=common} selects a completely generic processor. Code
|
||||
generated under this option will run on any POWER or PowerPC processor.
|
||||
|
@ -7263,47 +7265,23 @@ The other options specify a specific processor. Code generated under
|
|||
those options will run best on that processor, and may not run at all on
|
||||
others.
|
||||
|
||||
The @option{-mcpu} options automatically enable or disable other
|
||||
@option{-m} options as follows:
|
||||
The @option{-mcpu} options automatically enable or disable the
|
||||
following options: @option{-maltivec}, @option{-mhard-float},
|
||||
@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
|
||||
@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
|
||||
@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
|
||||
@option{-mstring}. The particular options set for any particular CPU
|
||||
will vary between compiler versions, depending on what setting seems
|
||||
to produce optimal code for that CPU; it doesn't necessarily reflect
|
||||
the actual hardware's capabilities. If you wish to set an individual
|
||||
option to a particular value, you may specify it after the
|
||||
@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
|
||||
|
||||
@table @samp
|
||||
@item common
|
||||
@option{-mno-power}, @option{-mno-powerpc}
|
||||
|
||||
@item power
|
||||
@itemx power2
|
||||
@itemx rios1
|
||||
@itemx rios2
|
||||
@itemx rsc
|
||||
@option{-mpower}, @option{-mno-powerpc}, @option{-mno-new-mnemonics}
|
||||
|
||||
@item powerpc
|
||||
@itemx rs64a
|
||||
@itemx 602
|
||||
@itemx 603
|
||||
@itemx 603e
|
||||
@itemx 604
|
||||
@itemx 620
|
||||
@itemx 630
|
||||
@itemx 740
|
||||
@itemx 7400
|
||||
@itemx 7450
|
||||
@itemx G4
|
||||
@itemx 750
|
||||
@itemx G3
|
||||
@itemx 505
|
||||
@itemx 970
|
||||
@itemx G5
|
||||
@option{-mno-power}, @option{-mpowerpc}, @option{-mnew-mnemonics}
|
||||
|
||||
@item 601
|
||||
@option{-mpower}, @option{-mpowerpc}, @option{-mnew-mnemonics}
|
||||
|
||||
@item 403
|
||||
@itemx 821
|
||||
@itemx 860
|
||||
@option{-mno-power}, @option{-mpowerpc}, @option{-mnew-mnemonics}, @option{-msoft-float}
|
||||
@end table
|
||||
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
|
||||
not enabled or disabled by the @option{-mcpu} option at present, since
|
||||
AIX does not have full support for these options. You may still
|
||||
enable or disable them individually if you're sure it'll work in your
|
||||
environment.
|
||||
|
||||
@item -mtune=@var{cpu_type}
|
||||
@opindex mtune
|
||||
|
|
Loading…
Reference in New Issue