re PR target/62128 (Use vpalignr for AVX2 rotation)
PR target/62128 * config/i386/i386.c (expand_vec_perm_palignr): If op1, op0 order of palignr arguments can't be used due to min 0 or max - min too high, try also op0, op1 order of palignr arguments. * gcc.dg/torture/vshuf-16.inc (TESTS): Add 2 new permutations. * gcc.dg/torture/vshuf-32.inc (TESTS): Add 5 new permutations. From-SVN: r215834
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Jakub Jelinek
Jakub Jelinek
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661fb5ddb8
@ -1,3 +1,10 @@
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2014-10-03 Jakub Jelinek <jakub@redhat.com>
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PR target/62128
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* config/i386/i386.c (expand_vec_perm_palignr): If op1, op0 order
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of palignr arguments can't be used due to min 0 or max - min
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too high, try also op0, op1 order of palignr arguments.
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2014-10-02 Jan Hubicka <hubicka@ucw.cz>
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* cgraph.h (ipa_polymorphic_call_context):
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@ -43298,8 +43298,8 @@ static bool
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expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p)
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{
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unsigned i, nelt = d->nelt;
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unsigned min, max;
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bool in_order, ok;
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unsigned min, max, minswap, maxswap;
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bool in_order, ok, swap = false;
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rtx shift, target;
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struct expand_vec_perm_d dcopy;
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@ -43309,20 +43309,40 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p)
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&& (!TARGET_AVX2 || GET_MODE_SIZE (d->vmode) != 32))
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return false;
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min = 2 * nelt, max = 0;
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min = 2 * nelt;
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max = 0;
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minswap = 2 * nelt;
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maxswap = 0;
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for (i = 0; i < nelt; ++i)
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{
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unsigned e = d->perm[i];
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unsigned eswap = d->perm[i] ^ nelt;
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if (GET_MODE_SIZE (d->vmode) == 32)
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{
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e = (e & ((nelt / 2) - 1)) | ((e & nelt) >> 1);
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eswap = e ^ (nelt / 2);
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}
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if (e < min)
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min = e;
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if (e > max)
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max = e;
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if (eswap < minswap)
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minswap = eswap;
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if (eswap > maxswap)
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maxswap = eswap;
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}
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if (min == 0
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|| max - min >= (GET_MODE_SIZE (d->vmode) == 32 ? nelt / 2 : nelt))
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{
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if (d->one_operand_p
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|| minswap == 0
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|| maxswap - minswap >= (GET_MODE_SIZE (d->vmode) == 32
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? nelt / 2 : nelt))
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return false;
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swap = true;
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min = minswap;
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max = maxswap;
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}
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/* Given that we have SSSE3, we know we'll be able to implement the
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single operand permutation after the palignr with pshufb for
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@ -43332,6 +43352,13 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p)
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return true;
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dcopy = *d;
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if (swap)
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{
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dcopy.op0 = d->op1;
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dcopy.op1 = d->op0;
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for (i = 0; i < nelt; ++i)
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dcopy.perm[i] ^= nelt;
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}
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in_order = true;
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for (i = 0; i < nelt; ++i)
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@ -43365,14 +43392,16 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p)
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if (GET_MODE_SIZE (d->vmode) == 16)
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{
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target = gen_reg_rtx (TImode);
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emit_insn (gen_ssse3_palignrti (target, gen_lowpart (TImode, d->op1),
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gen_lowpart (TImode, d->op0), shift));
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emit_insn (gen_ssse3_palignrti (target, gen_lowpart (TImode, dcopy.op1),
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gen_lowpart (TImode, dcopy.op0), shift));
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}
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else
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{
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target = gen_reg_rtx (V2TImode);
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emit_insn (gen_avx2_palignrv2ti (target, gen_lowpart (V2TImode, d->op1),
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gen_lowpart (V2TImode, d->op0), shift));
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emit_insn (gen_avx2_palignrv2ti (target,
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gen_lowpart (V2TImode, dcopy.op1),
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gen_lowpart (V2TImode, dcopy.op0),
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shift));
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}
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dcopy.op0 = dcopy.op1 = gen_lowpart (d->vmode, target);
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@ -1,3 +1,9 @@
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2014-10-03 Jakub Jelinek <jakub@redhat.com>
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PR target/62128
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* gcc.dg/torture/vshuf-16.inc (TESTS): Add 2 new permutations.
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* gcc.dg/torture/vshuf-32.inc (TESTS): Add 5 new permutations.
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2014-10-02 Edward Smith-Rowland <3dw4rd@verizon.net>
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* g++.dg/cpp1y/feat-cxx98-neg.C: Fix double negative thinko and
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@ -23,7 +23,9 @@ T (19, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) \
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T (20, 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23) \
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T (21, 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31) \
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T (22, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0) \
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T (23, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15)
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T (23, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15) \
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T (24, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 1, 2, 3, 4, 5) \
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T (25, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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#define EXPTESTS \
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T (116, 28, 13, 27, 11, 21, 1, 5, 22, 29, 14, 15, 6, 3, 10, 16, 30) \
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T (117, 22, 26, 1, 13, 29, 3, 18, 18, 11, 21, 12, 28, 19, 5, 7, 4) \
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@ -23,7 +23,12 @@ T (19, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 1
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T (20, 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39, 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47) \
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T (21, 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55, 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63) \
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T (22, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0) \
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T (23, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 31)
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T (23, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 31) \
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T (24, 0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 2, 5, 8, 11, 14, 17, 20, 23, 26, 29) \
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T (25, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42) \
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T (26, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52) \
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T (27, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53) \
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T (28, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 0, 1, 2, 3, 4, 5, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 16, 17, 18, 19, 20, 21)
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#define EXPTESTS \
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T (116, 13, 38, 47, 3, 17, 8, 38, 20, 59, 61, 39, 26, 7, 49, 63, 43, 57, 16, 40, 19, 4, 32, 27, 7, 52, 19, 46, 55, 36, 41, 48, 6) \
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T (117, 39, 35, 59, 20, 56, 18, 58, 63, 57, 14, 2, 16, 5, 61, 35, 4, 53, 9, 52, 51, 27, 33, 61, 12, 3, 35, 36, 40, 37, 7, 45, 42) \
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