re PR target/35574 (unrecognizable insn generated for vector move)
PR target/35574 * config/sparc/constraints.md (D): New. * config/sparc/predicates.md (const_double_or_vector_operand): New. * config/sparc/sparc.c (sparc_extra_constraint_check): Handle the 'D' constraint. * config/sparc/sparc.md (*movdf_insn_sp32_v9, *movdf_insn_sp64): Use the 'D' constraint in addition to 'F' in some alternatives. (DF splitter): Generalize for V64mode. * doc/md.texi (SPARC): Document the 'D' constraint. From-SVN: r141644
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
1ddb9ec910
commit
66e62b4943
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@ -1,3 +1,16 @@
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2008-11-06 Kazu Hirata <kazu@codesourcery.com>
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PR target/35574
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* config/sparc/constraints.md (D): New.
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* config/sparc/predicates.md (const_double_or_vector_operand):
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New.
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* config/sparc/sparc.c (sparc_extra_constraint_check): Handle the
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'D' constraint.
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* config/sparc/sparc.md (*movdf_insn_sp32_v9, *movdf_insn_sp64):
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Use the 'D' constraint in addition to 'F' in some alternatives.
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(DF splitter): Generalize for V64mode.
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* doc/md.texi (SPARC): Document the 'D' constraint.
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2008-11-06 Uros Bizjak <ubizjak@gmail.com>
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* reg-stack.c (reg_to_stack): Generate +QNaN using real_nan.
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@ -100,6 +100,11 @@
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;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
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;; i.e. accept pseudo-registers during reload.
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(define_constraint "D"
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"const_vector"
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(and (match_code "const_vector")
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(match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT")))
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(define_constraint "Q"
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"Floating-point constant that can be loaded with a sethi instruction"
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(and (match_code "const_double")
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@ -83,6 +83,10 @@
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return fp_high_losum_p (op);
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})
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;; Return true if OP is a const_double or const_vector.
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(define_predicate "const_double_or_vector_operand"
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(match_code "const_double,const_vector"))
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;; Predicates for symbolic constants.
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@ -2571,7 +2571,7 @@
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;; We have available v9 double floats but not 64-bit integer registers.
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(define_insn "*movdf_insn_sp32_v9"
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[(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
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(match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYF,*rGYf"))]
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(match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
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"TARGET_FPU
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&& TARGET_V9
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&& ! TARGET_ARCH64
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@ -2612,7 +2612,7 @@
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;; We have available both v9 double floats and 64-bit integer registers.
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(define_insn "*movdf_insn_sp64"
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[(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
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(match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,F"))]
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(match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
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"TARGET_FPU
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&& TARGET_ARCH64
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&& (register_operand (operands[0], <V64:MODE>mode)
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@ -2643,22 +2643,17 @@
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stx\t%r1, %0"
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[(set_attr "type" "*,load,store")])
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;; This pattern build DFmode constants in integer registers.
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;; This pattern builds V64mode constants in integer registers.
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(define_split
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[(set (match_operand:DF 0 "register_operand" "")
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(match_operand:DF 1 "const_double_operand" ""))]
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[(set (match_operand:V64 0 "register_operand" "")
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(match_operand:V64 1 "const_double_or_vector_operand" ""))]
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"TARGET_FPU
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&& (GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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&& ! const_zero_operand(operands[1], DFmode)
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&& ! const_zero_operand (operands[1], GET_MODE (operands[0]))
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&& reload_completed"
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[(clobber (const_int 0))]
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{
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REAL_VALUE_TYPE r;
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long l[2];
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REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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REAL_VALUE_TO_TARGET_DOUBLE (r, l);
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operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
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if (TARGET_ARCH64)
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@ -2666,31 +2661,34 @@
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#if HOST_BITS_PER_WIDE_INT == 32
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gcc_unreachable ();
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#else
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HOST_WIDE_INT val;
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val = ((HOST_WIDE_INT)(unsigned long)l[1] |
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((HOST_WIDE_INT)(unsigned long)l[0] << 32));
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emit_insn (gen_movdi (operands[0], gen_int_mode (val, DImode)));
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enum machine_mode mode = GET_MODE (operands[1]);
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rtx tem = simplify_subreg (DImode, operands[1], mode, 0);
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emit_insn (gen_movdi (operands[0], tem));
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#endif
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}
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else
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{
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emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
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gen_int_mode (l[0], SImode)));
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enum machine_mode mode = GET_MODE (operands[1]);
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rtx hi = simplify_subreg (SImode, operands[1], mode, 0);
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rtx lo = simplify_subreg (SImode, operands[1], mode, 4);
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gcc_assert (GET_CODE (hi) == CONST_INT);
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gcc_assert (GET_CODE (lo) == CONST_INT);
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emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), hi));
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/* Slick... but this trick loses if this subreg constant part
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can be done in one insn. */
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if (l[1] == l[0]
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&& ! SPARC_SETHI32_P (l[0])
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&& ! SPARC_SIMM13_P (l[0]))
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if (lo == hi
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&& ! SPARC_SETHI32_P (INTVAL (hi))
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&& ! SPARC_SIMM13_P (INTVAL (hi)))
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{
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emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
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gen_highpart (SImode, operands[0])));
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}
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else
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{
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emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
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gen_int_mode (l[1], SImode)));
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emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), lo));
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}
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}
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DONE;
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@ -2738,6 +2738,9 @@ when the Visual Instruction Set is available.
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@item h
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64-bit global or out register for the SPARC-V8+ architecture.
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@item D
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A vector constant
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@item I
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Signed 13-bit constant
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