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predicates.md (zero_operand, [...]): New predicates.

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* arm/predicates.md (zero_operand, reg_or_zero_operand): New predicates.
* arm/neon.md (neon_vceq<mode>, neon_vcge<mode>): Use
reg_or_zero_operand predicate.
(neon_vcle<mode>, neon_vclt<mode>): Use zero_operand predicate.

From-SVN: r185573
This commit is contained in:
Richard Earnshaw 2012-03-20 14:11:05 +00:00 committed by Richard Earnshaw
parent 7dc3263c69
commit 681676df51
3 changed files with 21 additions and 5 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2012-03-20 Richard Earnshaw <rearnsha@arm.com>
* arm/predicates.md (zero_operand, reg_or_zero_operand): New predicates.
* arm/neon.md (neon_vceq<mode>, neon_vcge<mode>): Use
reg_or_zero_operand predicate.
(neon_vcle<mode>, neon_vclt<mode>): Use zero_operand predicate.
2012-03-20 Jakub Jelinek <jakub@redhat.com> 2012-03-20 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.c (ix86_decompose_address) <case ZERO_EXTEND>: * config/i386/i386.c (ix86_decompose_address) <case ZERO_EXTEND>:

10
gcc/config/arm/neon.md
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@ -2114,7 +2114,7 @@
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
(unspec:<V_cmp_result> (unspec:<V_cmp_result>
[(match_operand:VDQW 1 "s_register_operand" "w,w") [(match_operand:VDQW 1 "s_register_operand" "w,w")
(match_operand:VDQW 2 "nonmemory_operand" "w,Dz") (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")
(match_operand:SI 3 "immediate_operand" "i,i")] (match_operand:SI 3 "immediate_operand" "i,i")]
UNSPEC_VCEQ))] UNSPEC_VCEQ))]
"TARGET_NEON" "TARGET_NEON"
@ -2133,7 +2133,7 @@
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
(unspec:<V_cmp_result> (unspec:<V_cmp_result>
[(match_operand:VDQW 1 "s_register_operand" "w,w") [(match_operand:VDQW 1 "s_register_operand" "w,w")
(match_operand:VDQW 2 "nonmemory_operand" "w,Dz") (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")
(match_operand:SI 3 "immediate_operand" "i,i")] (match_operand:SI 3 "immediate_operand" "i,i")]
UNSPEC_VCGE))] UNSPEC_VCGE))]
"TARGET_NEON" "TARGET_NEON"
@ -2164,7 +2164,7 @@
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
(unspec:<V_cmp_result> (unspec:<V_cmp_result>
[(match_operand:VDQW 1 "s_register_operand" "w,w") [(match_operand:VDQW 1 "s_register_operand" "w,w")
(match_operand:VDQW 2 "nonmemory_operand" "w,Dz") (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")
(match_operand:SI 3 "immediate_operand" "i,i")] (match_operand:SI 3 "immediate_operand" "i,i")]
UNSPEC_VCGT))] UNSPEC_VCGT))]
"TARGET_NEON" "TARGET_NEON"
@ -2198,7 +2198,7 @@
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
(unspec:<V_cmp_result> (unspec:<V_cmp_result>
[(match_operand:VDQW 1 "s_register_operand" "w") [(match_operand:VDQW 1 "s_register_operand" "w")
(match_operand:VDQW 2 "nonmemory_operand" "Dz") (match_operand:VDQW 2 "zero_operand" "Dz")
(match_operand:SI 3 "immediate_operand" "i")] (match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VCLE))] UNSPEC_VCLE))]
"TARGET_NEON" "TARGET_NEON"
@ -2215,7 +2215,7 @@
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
(unspec:<V_cmp_result> (unspec:<V_cmp_result>
[(match_operand:VDQW 1 "s_register_operand" "w") [(match_operand:VDQW 1 "s_register_operand" "w")
(match_operand:VDQW 2 "nonmemory_operand" "Dz") (match_operand:VDQW 2 "zero_operand" "Dz")
(match_operand:SI 3 "immediate_operand" "i")] (match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VCLT))] UNSPEC_VCLT))]
"TARGET_NEON" "TARGET_NEON"

9
gcc/config/arm/predicates.md
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@ -89,6 +89,15 @@
&& REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
}) })
(define_predicate "zero_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST0_RTX (mode)")))
;; Match a register, or zero in the appropriate mode.
(define_predicate "reg_or_zero_operand"
(ior (match_operand 0 "s_register_operand")
(match_operand 0 "zero_operand")))
(define_special_predicate "subreg_lowpart_operator" (define_special_predicate "subreg_lowpart_operator"
(and (match_code "subreg") (and (match_code "subreg")
(match_test "subreg_lowpart_p (op)"))) (match_test "subreg_lowpart_p (op)")))