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i386.c (ix86_issue_rate): Pentium4, Nocona has issue rate of 2. 

* i386.c (ix86_issue_rate): Pentium4, Nocona has issue rate of 2.
	Core2, Corei7 and Haswell has issue rate of 4.
	(ix86_adjust_cost): Remove ATOM case; fix core2/corei7/Haswell case.

From-SVN: r203172
This commit is contained in:
Jan Hubicka 2013-10-03 19:27:32 +02:00 committed by Jan Hubicka
parent c7f36d55a6
commit 6867e128b9
2 changed files with 42 additions and 6 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2013-10-03 Jan Hubicka <jh@suse.cz>
* i386.c (ix86_issue_rate): Pentium4, Nocona has issue rate of 2.
Core2, Corei7 and Haswell has issue rate of 4.
(ix86_adjust_cost): Remove ATOM case; fix core2/corei7/Haswell case.
2013-10-03 Jan Hubicka <jh@suse.cz>
* i386.c (ix86_option_override_internal): Do not enable

42
gcc/config/i386/i386.c
View File

@ -24418,17 +24418,14 @@ ix86_issue_rate (void)
case PROCESSOR_SLM:
case PROCESSOR_K6:
case PROCESSOR_BTVER2:
case PROCESSOR_PENTIUM4:
case PROCESSOR_NOCONA:
return 2;
case PROCESSOR_PENTIUMPRO:
case PROCESSOR_PENTIUM4:
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
case PROCESSOR_HASWELL:
case PROCESSOR_ATHLON:
case PROCESSOR_K8:
case PROCESSOR_AMDFAM10:
case PROCESSOR_NOCONA:
case PROCESSOR_GENERIC:
case PROCESSOR_BDVER1:
case PROCESSOR_BDVER2:
@ -24436,6 +24433,11 @@ ix86_issue_rate (void)
case PROCESSOR_BTVER1:
return 3;
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
case PROCESSOR_HASWELL:
return 4;
default:
return 1;
}
@ -24692,10 +24694,15 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case PROCESSOR_BDVER3:
case PROCESSOR_BTVER1:
case PROCESSOR_BTVER2:
case PROCESSOR_ATOM:
case PROCESSOR_GENERIC:
memory = get_attr_memory (insn);
/* Stack engine allows to execute push&pop instructions in parall. */
if (((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
&& (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
&& (ix86_tune != PROCESSOR_ATHLON && ix86_tune != PROCESSOR_K8))
return 0;
/* Show ability of reorder buffer to hide latency of load by executing
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
@ -24722,6 +24729,29 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
}
break;
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
case PROCESSOR_HASWELL:
memory = get_attr_memory (insn);
/* Stack engine allows to execute push&pop instructions in parall. */
if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
&& (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
return 0;
/* Show ability of reorder buffer to hide latency of load by executing
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
&& !ix86_agi_dependent (dep_insn, insn))
{
if (cost >= 4)
cost -= 4;
else
cost = 0;
}
break;
case PROCESSOR_SLM:
if (!reload_completed)
return cost;