arm - use the new CPU alias option to simplify the list of CPUs.
This patch simplifies the table of CPUs supported in GCC by making use of the new alias feature. Most of the changes are fairly straight-forward: - arm7tdmi and arm7tdmi-s are the same thing. - arm710t, arm720t and arm740t differ only in features external to the core - arm920 and arm920t are the same thing; arm922t and arm940t differ from arm920t only in features external to the core; ep9312 is an arm920t-derived core that we continue to recognize for legacy reasons. - arm10tdmi and arm1020t differ only in features external to the core. - arm9e, arm946te-s, arm966e-s and arm968e-s differ only in features external to the core. - arm10e, arm1020e and arm1022e differ only in features external to the core. The arm10e/arm1020e/arm1022e change is the only one which changes behaviour of the compiler slightly. Previously, and for no reason that I can remember, the scheduler for arm1020e/arm1022e was not used for arm10e: this was probably an oversight. The unification means that the same scheduler is now used for all three cores. * config/arm/arm-cpus.in (arm7tdmi): Add an alias for arm7tdmi-s. (arm7tdmi-s): Delete CPU. (arm710t): Add aliases for arm720t and arm740t. (arm720t, arm740t): Delete CPUs. (arm920t): Add aliases for arm920, arm922t and arm940t. (arm920, arm922t, arm940t): Delete CPUs. (arm10tdmi): Add alias for arm1020t. (arm1020t): Delete CPU. (arm9e): Add aliases for arm946e-s, arm966e-s and arm968e-s. (arm946e-s, arm966e-s, arm968e-s): Delete CPUs. (arm10e): Add aliases for arm1020e and arm1022e. (arm1020e, arm1022e): Delete CPU. * config/arm/arm.md (generic_sched): Remove entries that are now handled by aliases. (generic_vfp): Likewise. * config/arm/arm1020e.md: Simplify tuning selection based on alias changes. * config/arm/arm-tune.md: Regenerated. * config/arm/arm-tables.opt: Regenerated. From-SVN: r265960
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
1dd6990226
commit
69104d52dd
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@ -1,3 +1,25 @@
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2018-11-09 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm-cpus.in (arm7tdmi): Add an alias for arm7tdmi-s.
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(arm7tdmi-s): Delete CPU.
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(arm710t): Add aliases for arm720t and arm740t.
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(arm720t, arm740t): Delete CPUs.
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(arm920t): Add aliases for arm920, arm922t and arm940t.
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(arm920, arm922t, arm940t): Delete CPUs.
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(arm10tdmi): Add alias for arm1020t.
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(arm1020t): Delete CPU.
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(arm9e): Add aliases for arm946e-s, arm966e-s and arm968e-s.
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(arm946e-s, arm966e-s, arm968e-s): Delete CPUs.
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(arm10e): Add aliases for arm1020e and arm1022e.
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(arm1020e, arm1022e): Delete CPU.
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* config/arm/arm.md (generic_sched): Remove entries that are now
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handled by aliases.
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(generic_vfp): Likewise.
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* config/arm/arm1020e.md: Simplify tuning selection based on alias
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changes.
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* config/arm/arm-tune.md: Regenerated.
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* config/arm/arm-tables.opt: Regenerated.
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2018-11-09 Richard Biener <rguenther@suse.de>
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PR tree-optimization/87621
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@ -683,36 +683,19 @@ end cpu fa626
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# V4T Architecture Processors
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begin cpu arm7tdmi
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alias arm7tdmi-s
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tune flags CO_PROC
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architecture armv4t
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costs fastmul
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end cpu arm7tdmi
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begin cpu arm7tdmi-s
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cname arm7tdmis
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tune flags CO_PROC
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architecture armv4t
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costs fastmul
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end cpu arm7tdmi-s
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begin cpu arm710t
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alias arm720t arm740t
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tune flags WBUF
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architecture armv4t
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costs fastmul
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end cpu arm710t
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begin cpu arm720t
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tune flags WBUF
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architecture armv4t
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costs fastmul
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end cpu arm720t
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begin cpu arm740t
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tune flags WBUF
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architecture armv4t
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costs fastmul
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end cpu arm740t
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begin cpu arm9
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tune flags LDSCHED
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architecture armv4t
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@ -725,105 +708,41 @@ begin cpu arm9tdmi
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costs fastmul
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end cpu arm9tdmi
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begin cpu arm920
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tune flags LDSCHED
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architecture armv4t
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costs fastmul
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end cpu arm920
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begin cpu arm920t
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alias arm920 arm922t arm940t ep9312
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tune flags LDSCHED
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architecture armv4t
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costs fastmul
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end cpu arm920t
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begin cpu arm922t
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tune flags LDSCHED
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architecture armv4t
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costs fastmul
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end cpu arm922t
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begin cpu arm940t
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tune flags LDSCHED
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architecture armv4t
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costs fastmul
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end cpu arm940t
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begin cpu ep9312
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tune flags LDSCHED
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architecture armv4t
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costs fastmul
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end cpu ep9312
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# V5T Architecture Processors
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# These used VFPv1 which isn't supported by GCC
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begin cpu arm10tdmi
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alias arm1020t
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tune flags LDSCHED
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architecture armv5t
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costs fastmul
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end cpu arm10tdmi
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begin cpu arm1020t
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tune flags LDSCHED
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architecture armv5t
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costs fastmul
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end cpu arm1020t
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# V5TE Architecture Processors
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begin cpu arm9e
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alias arm946e-s arm966e-s arm968e-s
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm9e
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begin cpu arm946e-s
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cname arm946es
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm946e-s
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begin cpu arm966e-s
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cname arm966es
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm966e-s
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begin cpu arm968e-s
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cname arm968es
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs 9e
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end cpu arm968e-s
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begin cpu arm10e
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alias arm1020e arm1022e
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs fastmul
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end cpu arm10e
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begin cpu arm1020e
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs fastmul
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end cpu arm1020e
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begin cpu arm1022e
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tune flags LDSCHED
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architecture armv5te+fp
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option nofp remove ALL_FP
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costs fastmul
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end cpu arm1022e
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begin cpu xscale
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tune flags LDSCHED XSCALE
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architecture armv5te
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@ -42,66 +42,27 @@ Enum(processor_type) String(fa626) Value( TARGET_CPU_fa626)
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EnumValue
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Enum(processor_type) String(arm7tdmi) Value( TARGET_CPU_arm7tdmi)
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EnumValue
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Enum(processor_type) String(arm7tdmi-s) Value( TARGET_CPU_arm7tdmis)
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EnumValue
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Enum(processor_type) String(arm710t) Value( TARGET_CPU_arm710t)
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EnumValue
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Enum(processor_type) String(arm720t) Value( TARGET_CPU_arm720t)
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EnumValue
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Enum(processor_type) String(arm740t) Value( TARGET_CPU_arm740t)
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EnumValue
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Enum(processor_type) String(arm9) Value( TARGET_CPU_arm9)
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EnumValue
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Enum(processor_type) String(arm9tdmi) Value( TARGET_CPU_arm9tdmi)
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EnumValue
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Enum(processor_type) String(arm920) Value( TARGET_CPU_arm920)
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EnumValue
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Enum(processor_type) String(arm920t) Value( TARGET_CPU_arm920t)
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EnumValue
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Enum(processor_type) String(arm922t) Value( TARGET_CPU_arm922t)
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EnumValue
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Enum(processor_type) String(arm940t) Value( TARGET_CPU_arm940t)
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EnumValue
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Enum(processor_type) String(ep9312) Value( TARGET_CPU_ep9312)
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EnumValue
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Enum(processor_type) String(arm10tdmi) Value( TARGET_CPU_arm10tdmi)
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EnumValue
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Enum(processor_type) String(arm1020t) Value( TARGET_CPU_arm1020t)
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EnumValue
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Enum(processor_type) String(arm9e) Value( TARGET_CPU_arm9e)
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EnumValue
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Enum(processor_type) String(arm946e-s) Value( TARGET_CPU_arm946es)
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EnumValue
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Enum(processor_type) String(arm966e-s) Value( TARGET_CPU_arm966es)
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EnumValue
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Enum(processor_type) String(arm968e-s) Value( TARGET_CPU_arm968es)
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EnumValue
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Enum(processor_type) String(arm10e) Value( TARGET_CPU_arm10e)
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EnumValue
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Enum(processor_type) String(arm1020e) Value( TARGET_CPU_arm1020e)
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EnumValue
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Enum(processor_type) String(arm1022e) Value( TARGET_CPU_arm1022e)
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EnumValue
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Enum(processor_type) String(xscale) Value( TARGET_CPU_xscale)
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@ -23,32 +23,28 @@
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(define_attr "tune"
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"arm8,arm810,strongarm,
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fa526,fa626,arm7tdmi,
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arm7tdmis,arm710t,arm720t,
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arm740t,arm9,arm9tdmi,
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arm920,arm920t,arm922t,
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arm940t,ep9312,arm10tdmi,
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arm1020t,arm9e,arm946es,
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arm966es,arm968es,arm10e,
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arm1020e,arm1022e,xscale,
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iwmmxt,iwmmxt2,fa606te,
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fa626te,fmp626,fa726te,
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arm926ejs,arm1026ejs,arm1136js,
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arm1136jfs,arm1176jzs,arm1176jzfs,
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mpcorenovfp,mpcore,arm1156t2s,
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arm1156t2fs,cortexm1,cortexm0,
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cortexm0plus,cortexm1smallmultiply,cortexm0smallmultiply,
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cortexm0plussmallmultiply,genericv7a,cortexa5,
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cortexa7,cortexa8,cortexa9,
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cortexa12,cortexa15,cortexa17,
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cortexr4,cortexr4f,cortexr5,
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cortexr7,cortexr8,cortexm7,
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cortexm4,cortexm3,marvell_pj4,
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cortexa15cortexa7,cortexa17cortexa7,cortexa32,
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cortexa35,cortexa53,cortexa57,
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cortexa72,cortexa73,exynosm1,
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xgene1,cortexa57cortexa53,cortexa72cortexa53,
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cortexa73cortexa35,cortexa73cortexa53,cortexa55,
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cortexa75,cortexa76,ares,
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cortexa75cortexa55,cortexa76cortexa55,cortexm23,
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cortexm33,cortexr52"
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arm710t,arm9,arm9tdmi,
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arm920t,arm10tdmi,arm9e,
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arm10e,xscale,iwmmxt,
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iwmmxt2,fa606te,fa626te,
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fmp626,fa726te,arm926ejs,
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arm1026ejs,arm1136js,arm1136jfs,
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arm1176jzs,arm1176jzfs,mpcorenovfp,
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mpcore,arm1156t2s,arm1156t2fs,
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cortexm1,cortexm0,cortexm0plus,
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cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
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genericv7a,cortexa5,cortexa7,
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cortexa8,cortexa9,cortexa12,
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cortexa15,cortexa17,cortexr4,
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cortexr4f,cortexr5,cortexr7,
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cortexr8,cortexm7,cortexm4,
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cortexm3,marvell_pj4,cortexa15cortexa7,
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cortexa17cortexa7,cortexa32,cortexa35,
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cortexa53,cortexa57,cortexa72,
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cortexa73,exynosm1,xgene1,
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cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
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cortexa73cortexa53,cortexa55,cortexa75,
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cortexa76,ares,cortexa75cortexa55,
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cortexa76cortexa55,cortexm23,cortexm33,
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cortexr52"
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(const (symbol_ref "((enum attr_tune) arm_tune)")))
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@ -384,7 +384,7 @@
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(define_attr "generic_sched" "yes,no"
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(const (if_then_else
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(ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,\
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arm926ejs,arm1020e,arm1026ejs,arm1136js,\
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arm926ejs,arm10e,arm1026ejs,arm1136js,\
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arm1136jfs,cortexa5,cortexa7,cortexa8,\
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cortexa9,cortexa12,cortexa15,cortexa17,\
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cortexa53,cortexa57,cortexm4,cortexm7,\
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@ -396,7 +396,7 @@
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(define_attr "generic_vfp" "yes,no"
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(const (if_then_else
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(and (eq_attr "fpu" "vfp")
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(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
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(eq_attr "tune" "!arm10e,cortexa5,cortexa7,\
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cortexa8,cortexa9,cortexa53,cortexm4,\
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cortexm7,marvell_pj4,xgene1")
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(eq_attr "tune_cortexr4" "no"))
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@ -65,7 +65,7 @@
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;; ALU operations with no shifted operand
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(define_insn_reservation "1020alu_op" 1
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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alu_sreg,alus_sreg,logic_reg,logics_reg,\
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adc_imm,adcs_imm,adc_reg,adcs_reg,\
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;; ALU operations with a shift-by-constant operand
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(define_insn_reservation "1020alu_shift_op" 1
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
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logic_shift_imm,logics_shift_imm,\
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extend,mov_shift,mvn_shift"))
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;; the shift value in a second cycle. Pretend we take two cycles in
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;; the execute stage.
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(define_insn_reservation "1020alu_shift_reg_op" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
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logic_shift_reg,logics_shift_reg,\
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mov_shift_reg,mvn_shift_reg"))
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;; The result of the "smul" and "smulw" instructions is not available
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;; until after the memory stage.
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(define_insn_reservation "1020mult1" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "smulxy,smulwy"))
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"1020a_e,1020a_m,1020a_w")
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;; the execute stage; the result is available immediately following
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;; the execute stage.
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(define_insn_reservation "1020mult2" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "smlaxy,smlalxy,smlawx"))
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"1020a_e*2,1020a_m,1020a_w")
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;; through the execute stage; the result is not available until after
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;; the memory stage.
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(define_insn_reservation "1020mult3" 3
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "smlalxy,mul,mla"))
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"1020a_e*2,1020a_m,1020a_w")
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;; four iterations in order to set the flags. The value result is
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;; available after three iterations.
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(define_insn_reservation "1020mult4" 3
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "muls,mlas"))
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"1020a_e*4,1020a_m,1020a_w")
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;; three iterations through the execute cycle, and make their results
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;; available after the memory cycle.
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(define_insn_reservation "1020mult5" 4
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(and (eq_attr "tune" "arm10e")
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(eq_attr "type" "umull,umlal,smull,smlal"))
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"1020a_e*3,1020a_m,1020a_w")
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@ -152,7 +152,7 @@
|
|||
;; the execute stage for five iterations in order to set the flags.
|
||||
;; The value result is available after four iterations.
|
||||
(define_insn_reservation "1020mult6" 4
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "umulls,umlals,smulls,smlals"))
|
||||
"1020a_e*5,1020a_m,1020a_w")
|
||||
|
||||
|
|
@ -175,12 +175,12 @@
|
|||
;; For 4byte loads there is a bypass from the load stage
|
||||
|
||||
(define_insn_reservation "1020load1_op" 2
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "load_byte,load_4"))
|
||||
"1020a_e+1020l_e,1020l_m,1020l_w")
|
||||
|
||||
(define_insn_reservation "1020store1_op" 0
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "store_4"))
|
||||
"1020a_e+1020l_e,1020l_m,1020l_w")
|
||||
|
||||
|
|
@ -210,22 +210,22 @@
|
|||
;; PC, there are additional stalls; that is not modeled.
|
||||
|
||||
(define_insn_reservation "1020load2_op" 2
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "load_8"))
|
||||
"1020a_e+1020l_e,1020l_m,1020l_w")
|
||||
|
||||
(define_insn_reservation "1020store2_op" 0
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "store_8"))
|
||||
"1020a_e+1020l_e,1020l_m,1020l_w")
|
||||
|
||||
(define_insn_reservation "1020load34_op" 3
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "load_12,load_16"))
|
||||
"1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
|
||||
|
||||
(define_insn_reservation "1020store34_op" 0
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "store_12,store_16"))
|
||||
"1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
|
||||
|
||||
|
|
@ -242,7 +242,7 @@
|
|||
;; therefore the minimum value.
|
||||
|
||||
(define_insn_reservation "1020branch_op" 0
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "branch"))
|
||||
"1020a_e")
|
||||
|
||||
|
|
@ -251,7 +251,7 @@
|
|||
;; than that.
|
||||
|
||||
(define_insn_reservation "1020call_op" 32
|
||||
(and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "type" "call"))
|
||||
"1020a_e*4")
|
||||
|
||||
|
|
@ -272,7 +272,7 @@
|
|||
(exclusion_set "v10_fmac,v10_ds" "v10_fmstat")
|
||||
|
||||
(define_attr "vfp10" "yes,no"
|
||||
(const (if_then_else (and (eq_attr "tune" "arm1020e,arm1022e")
|
||||
(const (if_then_else (and (eq_attr "tune" "arm10e")
|
||||
(eq_attr "fpu" "vfp"))
|
||||
(const_string "yes") (const_string "no"))))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue