Add combine splitter to transform vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0
gcc/ChangeLog: PR target/100738 * config/i386/sse.md (*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_not_ltint): Add new define_insn_and_split. gcc/testsuite/ChangeLog: PR target/100738 * g++.target/i386/pr100738-1.C: New test.
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@ -20767,6 +20767,33 @@
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(set_attr "btver2_decode" "vector,vector,vector")
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(set_attr "mode" "<ssefltvecmode>")])
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;; PR target/100738: Transform vpcmpeqd + vpxor + vblendvps to vblendvps for inverted mask;
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(define_insn_and_split "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_not_ltint"
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[(set (match_operand:<ssebytemode> 0 "register_operand")
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(unspec:<ssebytemode>
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[(match_operand:<ssebytemode> 1 "register_operand")
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(match_operand:<ssebytemode> 2 "vector_operand")
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(subreg:<ssebytemode>
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(lt:VI48_AVX
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(subreg:VI48_AVX
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(not:<ssebytemode>
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(match_operand:<ssebytemode> 3 "register_operand")) 0)
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(match_operand:VI48_AVX 4 "const0_operand")) 0)]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1 && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(unspec:<ssefltvecmode>
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[(match_dup 2) (match_dup 1) (match_dup 3)] UNSPEC_BLENDV))]
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{
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operands[0] = gen_lowpart (<ssefltvecmode>mode, operands[0]);
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operands[1] = gen_lowpart (<ssefltvecmode>mode, operands[1]);
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operands[2] = force_reg (<ssefltvecmode>mode,
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gen_lowpart (<ssefltvecmode>mode, operands[2]));
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operands[3] = gen_lowpart (<ssefltvecmode>mode, operands[3]);
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})
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(define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>"
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[(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x")
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(unspec:VF_128_256
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gcc/testsuite/g++.target/i386/pr100738-1.C
Executable file
19
gcc/testsuite/g++.target/i386/pr100738-1.C
Executable file
@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* { dg-options "-Ofast -mavx2" } */
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/* { dg-final {scan-assembler-times "vblendvps\[ \\t\]" 2 } } */
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/* { dg-final {scan-assembler-not "vpcmpeqd\[ \\t\]" } } */
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/* { dg-final {scan-assembler-not "vpxor\[ \\t\]" } } */
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typedef int v4si __attribute__((vector_size(16)));
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typedef char v16qi __attribute__((vector_size(16)));
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v4si
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foo_1 (v16qi a, v4si b, v4si c, v4si d)
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{
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return ((v4si)~a) < 0 ? c : d;
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}
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v4si
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foo_2 (v16qi a, v4si b, v4si c, v4si d)
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{
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return ((v4si)~a) >= 0 ? c : d;
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}
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