From 69b23ad67f594ad866b833c827bec1f5f5cdce8d Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Tue, 4 Aug 2015 13:24:26 +0000 Subject: [PATCH] neon.md (neon_vget_lanev2di): Handle big-endian targets. 2015-08-04 Christophe Lyon * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian targets. From-SVN: r226574 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/neon.md | 17 ++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 41ccf74b890..49751a7eddc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-08-04 Christophe Lyon + + * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian + targets. + 2015-08-04 Nathan Sidwell * config/nvptx/nvptx.h (struct nvptx_pseudo_info): Delete. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 4af74ce96ed..b1bf26a9451 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2731,7 +2731,22 @@ (match_operand:SI 2 "immediate_operand" "")] "TARGET_NEON" { - int lane = INTVAL (operands[2]); + int lane; + +if (BYTES_BIG_ENDIAN) + { + /* The intrinsics are defined in terms of a model where the + element ordering in memory is vldm order, whereas the generic + RTL is defined in terms of a model where the element ordering + in memory is array order. Convert the lane number to conform + to this model. */ + unsigned int elt = INTVAL (operands[2]); + unsigned int reg_nelts = 2; + elt ^= reg_nelts - 1; + operands[2] = GEN_INT (elt); + } + + lane = INTVAL (operands[2]); gcc_assert ((lane ==0) || (lane == 1)); emit_move_insn (operands[0], lane == 0 ? gen_lowpart (DImode, operands[1])