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re PR target/32280 (_mm_srli_si128, heinous code for some shifts) 

PR target/32280
	* config/i386/sse.md ("sse2_ashlti", "sse2_lshrti3"): Move ...
	* config/i386/i386.md ("sse2_ashlti", "sse2_lshrti3"): ... to here.

testsuite/ChangeLog:
	
	PR target/32280
	* gcc.target/i386/pr32280.c: New test.

From-SVN: r125615
This commit is contained in:
Uros Bizjak 2007-06-11 12:13:00 +02:00 committed by Uros Bizjak
parent f1da2df1e9
commit 69c553ef2a
5 changed files with 60 additions and 26 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2007-06-11 Uros Bizjak <ubizjak@gmail.com>
PR target/32280
* config/i386/sse.md ("sse2_ashlti", "sse2_lshrti3"): Move ...
* config/i386/i386.md ("sse2_ashlti", "sse2_lshrti3"): ... to here.
2007-06-11 Uros Bizjak <ubizjak@gmail.com>
PR middle-end/32279

32
gcc/config/i386/i386.md
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@ -10317,6 +10317,22 @@
"#"
[(set_attr "type" "multi")])
;; This pattern must be defined before *ashlti3_2 to prevent
;; combine pass from converting sse2_ashlti3 to *ashlti3_2.
(define_insn "sse2_ashlti3"
[(set (match_operand:TI 0 "register_operand" "=x")
(ashift:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
"TARGET_SSE2"
{
operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
return "pslldq\t{%2, %0|%0, %2}";
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "*ashlti3_2"
[(set (match_operand:TI 0 "register_operand" "=r")
(ashift:TI (match_operand:TI 1 "register_operand" "0")
@ -11990,6 +12006,22 @@
"#"
[(set_attr "type" "multi")])
;; This pattern must be defined before *lshrti3_2 to prevent
;; combine pass from converting sse2_lshrti3 to *lshrti3_2.
(define_insn "sse2_lshrti3"
[(set (match_operand:TI 0 "register_operand" "=x")
(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
"TARGET_SSE2"
{
operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
return "psrldq\t{%2, %0|%0, %2}";
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "*lshrti3_2"
[(set (match_operand:TI 0 "register_operand" "=r")
(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")

26
gcc/config/i386/sse.md
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@ -3345,19 +3345,6 @@
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ashlti3"
[(set (match_operand:TI 0 "register_operand" "=x")
(ashift:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
"TARGET_SSE2"
{
operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
return "pslldq\t{%2, %0|%0, %2}";
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "vec_shl_<mode>"
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(ashift:TI (match_operand:SSEMODEI 1 "register_operand" "")
@ -3370,19 +3357,6 @@
operands[1] = gen_lowpart (TImode, operands[1]);
})
(define_insn "sse2_lshrti3"
[(set (match_operand:TI 0 "register_operand" "=x")
(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
"TARGET_SSE2"
{
operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
return "psrldq\t{%2, %0|%0, %2}";
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "vec_shr_<mode>"
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "")

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2007-06-11 Uros Bizjak <ubizjak@gmail.com>
PR target/32280
* gcc.target/i386/pr32280.c: New test.
2007-06-11 Uros Bizjak <ubizjak@gmail.com>
PR middle-end/32279

17
gcc/testsuite/gcc.target/i386/pr32280.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-O2 -msse2" } */
typedef long long __m128i __attribute__ ((__vector_size__ (16)));
__m128i foo1(__m128i __a)
{
return (__m128i)__builtin_ia32_pslldqi128 (__a, 8);
}
__m128i foo2(__m128i __a)
{
return (__m128i)__builtin_ia32_psrldqi128 (__a, 8);
}
/* { dg-final { scan-assembler "psrldq" } } */
/* { dg-final { scan-assembler "pslldq" } } */