re PR target/85358 (PowerPC: Using -mabi=ieeelongdouble -mcpu=power9 breaks __ibm128)
[gcc] 2018-06-18 Michael Meissner <meissner@linux.ibm.com> PR target/85358 * config/rs6000/rs6000-modes.def (toplevel): Rework the 128-bit floating point modes, so that IFmode is numerically greater than TFmode, which is greater than KFmode using FRACTIONAL_FLOAT_MODE to declare the ordering. This prevents IFmode from being converted to TFmode when long double is IEEE 128-bit on an ISA 3.0 machine. Include rs6000-modes.h to share the fractional values between genmodes* and the rest of the compiler. (IFmode): Likewise. (KFmode): Likewise. (TFmode): Likewise. * config/rs6000/rs6000-modes.h: New file. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Change the meaning of rs6000_long_double_size so that 126..128 selects an appropriate 128-bit floating point type. (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000.h (toplevel): Include rs6000-modes.h. (TARGET_LONG_DOUBLE_128): Change the meaning of rs6000_long_double_size so that 126..128 selects an appropriate 128-bit floating point type. (LONG_DOUBLE_TYPE_SIZE): Update comment. * config/rs6000/rs6000.md (trunciftf2): Correct the modes of the source and destination to match the standard usage. (truncifkf2): Likewise. (copysign<mode>3, IEEE iterator): Rework copysign of float128 on ISA 2.07 to use an explicit clobber, instead of passing in a temporary. (copysign<mode>3_soft): Likewise. [libgcc] 2018-06-18 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128 support modules with -mno-gnu-attribute. * config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise. From-SVN: r261712
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Michael Meissner
Michael Meissner
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6a8886e45f
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@ -1,3 +1,34 @@
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2018-06-18 Michael Meissner <meissner@linux.ibm.com>
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PR target/85358
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* config/rs6000/rs6000-modes.def (toplevel): Rework the 128-bit
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floating point modes, so that IFmode is numerically greater than
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TFmode, which is greater than KFmode using FRACTIONAL_FLOAT_MODE
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to declare the ordering. This prevents IFmode from being
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converted to TFmode when long double is IEEE 128-bit on an ISA 3.0
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machine. Include rs6000-modes.h to share the fractional values
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between genmodes* and the rest of the compiler.
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(IFmode): Likewise.
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(KFmode): Likewise.
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(TFmode): Likewise.
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* config/rs6000/rs6000-modes.h: New file.
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* config/rs6000/rs6000.c (rs6000_debug_reg_global): Change the
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meaning of rs6000_long_double_size so that 126..128 selects an
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appropriate 128-bit floating point type.
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(rs6000_option_override_internal): Likewise.
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* config/rs6000/rs6000.h (toplevel): Include rs6000-modes.h.
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(TARGET_LONG_DOUBLE_128): Change the meaning of
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rs6000_long_double_size so that 126..128 selects an appropriate
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128-bit floating point type.
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(LONG_DOUBLE_TYPE_SIZE): Update comment.
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* config/rs6000/rs6000.md (trunciftf2): Correct the modes of the
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source and destination to match the standard usage.
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(truncifkf2): Likewise.
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(copysign<mode>3, IEEE iterator): Rework copysign of float128 on
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ISA 2.07 to use an explicit clobber, instead of passing in a
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temporary.
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(copysign<mode>3_soft): Likewise.
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2018-06-18 David Malcolm <dmalcolm@redhat.com>
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* tree-vect-data-refs.c (vect_analyze_data_ref_dependences):
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@ -18,16 +18,39 @@
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* IBM 128-bit floating point. IFmode and KFmode use the fractional float
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support in order to declare 3 128-bit floating point types. */
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FRACTIONAL_FLOAT_MODE (IF, 106, 16, ibm_extended_format);
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/* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
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floating point) is the 128-bit floating point type with the highest
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precision (128 bits). This so that machine independent parts of the
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compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
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hardware support for IEEE 128-bit. We set TFmode (long double mode) in
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between, and KFmode (explicit __float128) below it.
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Previously, IFmode and KFmode were defined to be fractional modes and TFmode
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was the standard mode. Since IFmode does not define the normal arithmetic
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insns (other than neg/abs), on a ISA 3.0 system, the machine independent
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parts of the compiler would see that TFmode has the necessary hardware
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support, and widen the operation from IFmode to TFmode. However, IEEE
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128-bit is not strictly a super-set of IBM extended double and the
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conversion to/from IEEE 128-bit was a function call.
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We now make IFmode the highest fractional mode, which means its values are
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not considered for widening. Since we don't define insns for IFmode, the
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IEEE 128-bit modes would not widen to IFmode. */
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#ifndef RS6000_MODES_H
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#include "config/rs6000/rs6000-modes.h"
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#endif
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/* IBM 128-bit floating point. */
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FRACTIONAL_FLOAT_MODE (IF, FLOAT_PRECISION_IFmode, 16, ibm_extended_format);
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/* Explicit IEEE 128-bit floating point. */
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FRACTIONAL_FLOAT_MODE (KF, 113, 16, ieee_quad_format);
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FRACTIONAL_FLOAT_MODE (KF, FLOAT_PRECISION_KFmode, 16, ieee_quad_format);
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/* 128-bit floating point. ABI_V4 uses IEEE quad, AIX/Darwin
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adjust this in rs6000_option_override_internal. */
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FLOAT_MODE (TF, 16, ieee_quad_format);
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/* 128-bit floating point, either IBM 128-bit or IEEE 128-bit. This is
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adjusted in rs6000_option_override_internal to be the appropriate floating
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point type. */
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FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format);
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/* Add any extra modes needed to represent the condition code.
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@ -0,0 +1,36 @@
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/* Definitions 128-bit floating point precisions used by PowerPC.
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Copyright (C) 2018 Free Software Foundation, Inc.
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Contributed by Michael Meissner (meissner@linux.ibm.com)
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
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floating point) is the 128-bit floating point type with the highest
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precision (128 bits). This so that machine independent parts of the
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compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
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hardware support for IEEE 128-bit. We set TFmode (long double mode) in
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between, and KFmode (explicit __float128) below it.
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We won't encounter conversion from IEEE 128-bit to IBM 128-bit because we
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don't have insns to support the IBM 128-bit aritmetic operations. */
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#ifndef RS6000_MODES_H
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#define RS6000_MODES_H 1
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#define FLOAT_PRECISION_IFmode 128
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#define FLOAT_PRECISION_TFmode 127
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#define FLOAT_PRECISION_KFmode 126
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#endif /* RS6000_MODES_H */
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@ -2887,7 +2887,7 @@ rs6000_debug_reg_global (void)
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fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
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fprintf (stderr, DEBUG_FMT_D, "long_double_size",
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rs6000_long_double_type_size);
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if (rs6000_long_double_type_size == 128)
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if (rs6000_long_double_type_size > 64)
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{
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fprintf (stderr, DEBUG_FMT_S, "long double type",
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TARGET_IEEEQUAD ? "IEEE" : "IBM");
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@ -4558,16 +4558,25 @@ rs6000_option_override_internal (bool global_init_p)
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}
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}
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/* Use long double size to select the appropriate long double. We use
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TYPE_PRECISION to differentiate the 3 different long double types. We map
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128 into the precision used for TFmode. */
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int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
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? 64
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: FLOAT_PRECISION_TFmode);
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/* Set long double size before the IEEE 128-bit tests. */
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if (!global_options_set.x_rs6000_long_double_type_size)
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{
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if (main_target_opt != NULL
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&& (main_target_opt->x_rs6000_long_double_type_size
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!= RS6000_DEFAULT_LONG_DOUBLE_SIZE))
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!= default_long_double_size))
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error ("target attribute or pragma changes long double size");
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else
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rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
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rs6000_long_double_type_size = default_long_double_size;
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}
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else if (rs6000_long_double_type_size == 128)
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rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
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/* Set -mabi=ieeelongdouble on some old targets. In the future, power server
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systems will also set long double to be IEEE 128-bit. AIX and Darwin
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@ -30,6 +30,11 @@
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#include "config/rs6000/rs6000-opts.h"
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#endif
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/* 128-bit floating point precision values. */
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#ifndef RS6000_MODES_H
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#include "config/rs6000/rs6000-modes.h"
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#endif
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/* Definitions for the object file format. These are set at
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compile-time. */
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@ -539,7 +544,9 @@ extern int rs6000_vector_align[];
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#define TARGET_ALIGN_NATURAL 0
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#endif
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#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
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/* We use values 126..128 to pick the appropriate long double type (IFmode,
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KFmode, TFmode). */
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#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
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#define TARGET_IEEEQUAD rs6000_ieeequad
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#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
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#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
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@ -865,9 +872,8 @@ extern unsigned char rs6000_recip_bits[];
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words. */
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#define DOUBLE_TYPE_SIZE 64
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/* A C expression for the size in bits of the type `long double' on
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the target machine. If you don't define this, the default is two
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words. */
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/* A C expression for the size in bits of the type `long double' on the target
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machine. If you don't define this, the default is two words. */
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#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
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/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
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@ -8159,8 +8159,8 @@
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})
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(define_expand "trunciftf2"
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[(set (match_operand:IF 0 "gpc_reg_operand")
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(float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
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[(set (match_operand:TF 0 "gpc_reg_operand")
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(float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]
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"TARGET_FLOAT128_TYPE"
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{
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rs6000_expand_float128_convert (operands[0], operands[1], false);
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@ -8168,8 +8168,8 @@
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})
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(define_expand "truncifkf2"
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[(set (match_operand:IF 0 "gpc_reg_operand")
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(float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))]
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[(set (match_operand:KF 0 "gpc_reg_operand")
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(float_truncate:KF (match_operand:IF 1 "gpc_reg_operand")))]
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"TARGET_FLOAT128_TYPE"
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{
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rs6000_expand_float128_convert (operands[0], operands[1], false);
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@ -14102,11 +14102,8 @@
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emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
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operands[2]));
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else
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{
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rtx tmp = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
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operands[2], tmp));
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}
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emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
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operands[2]));
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DONE;
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})
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@ -14125,9 +14122,9 @@
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[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
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(unspec:IEEE128
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[(match_operand:IEEE128 1 "altivec_register_operand" "v")
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(match_operand:IEEE128 2 "altivec_register_operand" "v")
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(match_operand:IEEE128 3 "altivec_register_operand" "+v")]
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UNSPEC_COPYSIGN))]
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(match_operand:IEEE128 2 "altivec_register_operand" "v")]
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UNSPEC_COPYSIGN))
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(clobber (match_scratch:IEEE128 3 "=&v"))]
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"!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
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"xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
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[(set_attr "type" "veccomplex")
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@ -1,3 +1,9 @@
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2018-06-18 Michael Meissner <meissner@linux.ibm.com>
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* config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128
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support modules with -mno-gnu-attribute.
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* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.
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2018-06-07 Olivier Hainque <hainque@adacore.com>
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* config/t-vxworks (LIBGCC_INCLUDES): Add
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@ -59,7 +59,7 @@ fp128_includes = $(srcdir)/soft-fp/double.h \
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# Build the emulator without ISA 3.0 hardware support.
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FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
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-mno-float128-hardware \
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-mno-float128-hardware -mno-gnu-attribute \
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-I$(srcdir)/soft-fp \
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-I$(srcdir)/config/rs6000 \
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$(FLOAT128_HW_INSNS)
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@ -25,7 +25,7 @@ fp128_sed_hw = -hw
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# Build the hardware support functions with appropriate hardware support
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FP128_CFLAGS_HW = -Wno-type-limits -mvsx -mfloat128 \
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-mpower8-vector -mpower9-vector \
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-mfloat128-hardware \
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-mfloat128-hardware -mno-gnu-attribute \
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-I$(srcdir)/soft-fp \
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-I$(srcdir)/config/rs6000 \
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$(FLOAT128_HW_INSNS)
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