[PATCH][GCC] arm: Fix MVE scalar shift intrinsics code-gen.
This patch modifies the MVE scalar shift RTL patterns. The current patterns
have wrong constraints and predicates due to which the values returned from
MVE scalar shift instructions are overwritten in the code-gen.
example:
$ cat x.c
int32_t foo(int64_t acc, int shift)
{
return sqrshrl_sat48 (acc, shift);
}
Code-gen before applying this patch:
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve -mfloat-abi=hard -O2 -S
$ cat x.s
foo:
push {r4, r5}
sqrshrl r0, r1, #48, r2 ----> (a)
mov r0, r4 ----> (b)
pop {r4, r5}
bx lr
Code-gen after applying this patch:
foo:
sqrshrl r0, r1, #48, r2
bx lr
In the current compiler the return value (r0) from sqrshrl (a) is getting
overwritten by the mov statement (b).
This patch fixes above issue.
2020-06-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
gcc/
* config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate
and constraint of all the operands.
(mve_sqrshrl_sat<supf>_di): Likewise.
(mve_uqrshl_si): Likewise.
(mve_sqrshr_si): Likewise.
(mve_uqshll_di): Likewise.
(mve_urshrl_di): Likewise.
(mve_uqshl_si): Likewise.
(mve_urshr_si): Likewise.
(mve_sqshl_si): Likewise.
(mve_srshr_si): Likewise.
(mve_srshrl_di): Likewise.
(mve_sqshll_di): Likewise.
* config/arm/predicates.md (arm_low_register_operand): Define.
gcc/testsuite/
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: New test.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.
This commit is contained in:
Srinath Parvathaneni
parent
1160ec9a14
commit
6af598703f
@ -11344,9 +11344,9 @@
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;; [uqrshll_di]
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;;
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(define_insn "mve_uqrshll_sat<supf>_di"
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[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
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(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")]
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[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
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(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")]
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UQRSHLLQ))]
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"TARGET_HAVE_MVE"
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"uqrshll%?\\t%Q1, %R1, #<supf>, %2"
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@ -11356,9 +11356,9 @@
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;; [sqrshrl_di]
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;;
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(define_insn "mve_sqrshrl_sat<supf>_di"
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[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
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(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")]
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[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
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(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")]
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SQRSHRLQ))]
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"TARGET_HAVE_MVE"
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"sqrshrl%?\\t%Q1, %R1, #<supf>, %2"
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@ -11368,9 +11368,9 @@
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;; [uqrshl_si]
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;;
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(define_insn "mve_uqrshl_si"
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[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
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(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")]
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[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
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(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")]
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UQRSHL))]
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"TARGET_HAVE_MVE"
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"uqrshl%?\\t%1, %2"
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@ -11380,9 +11380,9 @@
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;; [sqrshr_si]
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;;
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(define_insn "mve_sqrshr_si"
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[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
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(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")]
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[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
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(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")]
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SQRSHR))]
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"TARGET_HAVE_MVE"
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"sqrshr%?\\t%1, %2"
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@ -11392,9 +11392,9 @@
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;; [uqshll_di]
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;;
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(define_insn "mve_uqshll_di"
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[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
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(us_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
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[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
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(us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")))]
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"TARGET_HAVE_MVE"
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"uqshll%?\\t%Q1, %R1, %2"
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[(set_attr "predicable" "yes")])
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@ -11403,9 +11403,9 @@
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;; [urshrl_di]
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;;
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(define_insn "mve_urshrl_di"
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[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
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(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
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[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
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(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")]
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URSHRL))]
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"TARGET_HAVE_MVE"
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"urshrl%?\\t%Q1, %R1, %2"
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@ -11415,9 +11415,9 @@
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;; [uqshl_si]
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;;
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(define_insn "mve_uqshl_si"
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[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
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(us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
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[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
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(us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")))]
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"TARGET_HAVE_MVE"
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"uqshl%?\\t%1, %2"
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[(set_attr "predicable" "yes")])
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@ -11426,9 +11426,9 @@
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;; [urshr_si]
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;;
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(define_insn "mve_urshr_si"
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[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
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(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
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[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
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(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")]
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URSHR))]
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"TARGET_HAVE_MVE"
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"urshr%?\\t%1, %2"
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@ -11438,9 +11438,9 @@
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;; [sqshl_si]
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;;
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(define_insn "mve_sqshl_si"
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[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
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(ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
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[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
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(ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")))]
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"TARGET_HAVE_MVE"
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"sqshl%?\\t%1, %2"
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[(set_attr "predicable" "yes")])
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@ -11449,9 +11449,9 @@
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;; [srshr_si]
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;;
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(define_insn "mve_srshr_si"
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[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
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(unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
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[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
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(unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")]
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SRSHR))]
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"TARGET_HAVE_MVE"
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"srshr%?\\t%1, %2"
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@ -11461,9 +11461,9 @@
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;; [srshrl_di]
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;;
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(define_insn "mve_srshrl_di"
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[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
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(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
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[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
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(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")]
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SRSHRL))]
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"TARGET_HAVE_MVE"
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"srshrl%?\\t%Q1, %R1, %2"
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@ -11473,9 +11473,9 @@
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;; [sqshll_di]
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;;
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(define_insn "mve_sqshll_di"
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[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
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(ss_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
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(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
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[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
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(ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "Pg")))]
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"TARGET_HAVE_MVE"
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"sqshll%?\\t%Q1, %R1, %2"
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[(set_attr "predicable" "yes")])
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@ -155,6 +155,18 @@
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|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
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})
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;; Low core register, or any pseudo.
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(define_predicate "arm_low_register_operand"
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(match_code "reg,subreg")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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return (REG_P (op)
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&& (REGNO (op) <= LAST_LO_REGNUM
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|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
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})
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(define_predicate "arm_general_adddi_operand"
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(ior (match_operand 0 "arm_general_register_operand")
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(and (match_code "const_int")
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@ -0,0 +1,40 @@
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/* { dg-do run } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-options "-O2" } */
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/* { dg-add-options arm_v8_1m_mve } */
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#include "arm_mve.h"
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#include "stdio.h"
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#include <stdlib.h>
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void
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foo (int64_t acc, int shift)
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{
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acc = sqrshrl_sat48 (acc, shift);
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if (acc != 16)
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abort();
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acc = sqrshrl (acc, shift);
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if (acc != 2)
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abort();
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}
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void
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foo1 (uint64_t acc, int shift)
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{
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acc = uqrshll_sat48 (acc, shift);
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if (acc != 16)
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abort();
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acc = uqrshll (acc, shift);
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if (acc != 128)
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abort();
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}
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int main()
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{
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int64_t acc = 128;
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uint64_t acc1 = 2;
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int shift = 3;
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foo (acc, shift);
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foo1 (acc1, shift);
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return 0;
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}
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@ -0,0 +1,35 @@
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/* { dg-do run } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-options "-O2" } */
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/* { dg-add-options arm_v8_1m_mve } */
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#include "arm_mve.h"
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#include "stdio.h"
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#include <stdlib.h>
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#define IMM 3
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void
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foo (int64_t acc, uint64_t acc1)
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{
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acc = sqshll (acc, IMM);
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if (acc != 128)
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abort();
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acc = srshrl (acc, IMM);
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if (acc != 16)
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abort();
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acc1 = uqshll (acc1, IMM);
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if (acc1 != 128)
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abort();
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acc1 = urshrl (acc1, IMM);
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if (acc1 != 16)
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abort();
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}
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int main()
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{
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int64_t acc = 16;
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uint64_t acc1 = 16;
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foo (acc, acc1);
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return 0;
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}
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@ -0,0 +1,28 @@
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/* { dg-do run } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-options "-O2" } */
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/* { dg-add-options arm_v8_1m_mve } */
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#include "arm_mve.h"
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#include "stdio.h"
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#include <stdlib.h>
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void
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foo (int32_t acc, uint32_t acc1, int shift)
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{
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acc = sqrshr (acc, shift);
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if (acc != 16)
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abort();
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acc1 = uqrshl (acc1, shift);
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if (acc1 != 128)
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abort();
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}
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int main()
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{
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int32_t acc = 128;
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uint32_t acc1 = 16;
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int shift = 3;
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foo (acc, acc1, shift);
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return 0;
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}
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@ -0,0 +1,34 @@
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/* { dg-do run } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-options "-O2" } */
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/* { dg-add-options arm_v8_1m_mve } */
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#include "arm_mve.h"
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#include <stdlib.h>
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#define IMM 3
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void
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foo (int32_t acc, uint32_t acc1)
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{
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acc = sqshl (acc, IMM);
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if (acc != 128)
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abort();
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acc = srshr (acc, IMM);
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if (acc != 16)
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abort();
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acc1 = uqshl (acc1, IMM);
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if (acc1 != 128)
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abort();
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acc1 = urshr (acc1, IMM);
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if (acc1 != 16)
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abort();
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}
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int main()
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{
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int32_t acc = 16;
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uint32_t acc1 = 16;
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foo (acc, acc1);
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return 0;
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}
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