sse.md (reduc_plus_scal_v8df, [...]): Merge into pattern reducing to half width and recursing and pattern terminating...
2018-10-10 Richard Biener <rguenther@suse.de> * config/i386/sse.md (reduc_plus_scal_v8df, reduc_plus_scal_v4df, reduc_plus_scal_v2df, reduc_plus_scal_v16sf, reduc_plus_scal_v8sf, reduc_plus_scal_v4sf): Merge into pattern reducing to half width and recursing and pattern terminating the recursion on SSE vector width using ix86_expand_reduc. (reduc_sminmax_scal_<mode>): Split into part reducing to half width and recursing and SSE2 vector variant doing the final reduction with ix86_expand_reduc. (reduc_uminmax_scal_<mode>): Likewise for the AVX512 variants with terminating the recursion at AVX level, splitting that to SSE there. From-SVN: r265004
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@ -1,3 +1,17 @@
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2018-10-10 Richard Biener <rguenther@suse.de>
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* config/i386/sse.md (reduc_plus_scal_v8df, reduc_plus_scal_v4df,
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reduc_plus_scal_v2df, reduc_plus_scal_v16sf, reduc_plus_scal_v8sf,
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reduc_plus_scal_v4sf): Merge into pattern reducing to half width
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and recursing and pattern terminating the recursion on SSE
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vector width using ix86_expand_reduc.
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(reduc_sminmax_scal_<mode>): Split into part reducing to half
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width and recursing and SSE2 vector variant doing the final
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reduction with ix86_expand_reduc.
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(reduc_uminmax_scal_<mode>): Likewise for the AVX512 variants
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with terminating the recursion at AVX level, splitting that
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to SSE there.
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2018-10-09 David Malcolm <dmalcolm@redhat.com>
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* genmatch.c (error_cb): Rename to...
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@ -2457,98 +2457,65 @@
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(set_attr "prefix_rep" "1,*")
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(set_attr "mode" "V4SF")])
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(define_expand "reduc_plus_scal_v8df"
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[(match_operand:DF 0 "register_operand")
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(match_operand:V8DF 1 "register_operand")]
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"TARGET_AVX512F"
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(define_mode_iterator REDUC_SSE_PLUS_MODE
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[(V2DF "TARGET_SSE") (V4SF "TARGET_SSE")])
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(define_expand "reduc_plus_scal_<mode>"
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[(plus:REDUC_SSE_PLUS_MODE
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(match_operand:<ssescalarmode> 0 "register_operand")
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(match_operand:REDUC_SSE_PLUS_MODE 1 "register_operand"))]
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""
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{
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rtx tmp = gen_reg_rtx (V8DFmode);
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ix86_expand_reduc (gen_addv8df3, tmp, operands[1]);
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emit_insn (gen_vec_extractv8dfdf (operands[0], tmp, const0_rtx));
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rtx tmp = gen_reg_rtx (<MODE>mode);
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ix86_expand_reduc (gen_add<mode>3, tmp, operands[1]);
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emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
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const0_rtx));
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DONE;
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})
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(define_expand "reduc_plus_scal_v4df"
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[(match_operand:DF 0 "register_operand")
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(match_operand:V4DF 1 "register_operand")]
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"TARGET_AVX"
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{
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rtx tmp = gen_reg_rtx (V2DFmode);
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emit_insn (gen_vec_extract_hi_v4df (tmp, operands[1]));
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rtx tmp2 = gen_reg_rtx (V2DFmode);
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emit_insn (gen_addv2df3 (tmp2, tmp, gen_lowpart (V2DFmode, operands[1])));
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rtx tmp3 = gen_reg_rtx (V2DFmode);
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emit_insn (gen_vec_interleave_highv2df (tmp3, tmp2, tmp2));
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emit_insn (gen_adddf3 (operands[0],
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gen_lowpart (DFmode, tmp2),
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gen_lowpart (DFmode, tmp3)));
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DONE;
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})
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(define_mode_iterator REDUC_PLUS_MODE
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[(V4DF "TARGET_AVX") (V8SF "TARGET_AVX")
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(V8DF "TARGET_AVX512F") (V16SF "TARGET_AVX512F")])
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(define_expand "reduc_plus_scal_v2df"
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[(match_operand:DF 0 "register_operand")
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(match_operand:V2DF 1 "register_operand")]
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"TARGET_SSE2"
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(define_expand "reduc_plus_scal_<mode>"
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[(plus:REDUC_PLUS_MODE
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(match_operand:<ssescalarmode> 0 "register_operand")
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(match_operand:REDUC_PLUS_MODE 1 "register_operand"))]
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""
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{
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rtx tmp = gen_reg_rtx (V2DFmode);
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emit_insn (gen_vec_interleave_highv2df (tmp, operands[1], operands[1]));
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emit_insn (gen_adddf3 (operands[0],
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gen_lowpart (DFmode, tmp),
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gen_lowpart (DFmode, operands[1])));
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DONE;
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})
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(define_expand "reduc_plus_scal_v16sf"
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[(match_operand:SF 0 "register_operand")
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(match_operand:V16SF 1 "register_operand")]
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"TARGET_AVX512F"
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{
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rtx tmp = gen_reg_rtx (V16SFmode);
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ix86_expand_reduc (gen_addv16sf3, tmp, operands[1]);
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emit_insn (gen_vec_extractv16sfsf (operands[0], tmp, const0_rtx));
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DONE;
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})
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(define_expand "reduc_plus_scal_v8sf"
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[(match_operand:SF 0 "register_operand")
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(match_operand:V8SF 1 "register_operand")]
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"TARGET_AVX"
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{
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rtx tmp = gen_reg_rtx (V8SFmode);
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rtx tmp2 = gen_reg_rtx (V8SFmode);
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rtx vec_res = gen_reg_rtx (V8SFmode);
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emit_insn (gen_avx_haddv8sf3 (tmp, operands[1], operands[1]));
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emit_insn (gen_avx_haddv8sf3 (tmp2, tmp, tmp));
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emit_insn (gen_avx_vperm2f128v8sf3 (tmp, tmp2, tmp2, GEN_INT (1)));
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emit_insn (gen_addv8sf3 (vec_res, tmp, tmp2));
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emit_insn (gen_vec_extractv8sfsf (operands[0], vec_res, const0_rtx));
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DONE;
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})
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(define_expand "reduc_plus_scal_v4sf"
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[(match_operand:SF 0 "register_operand")
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(match_operand:V4SF 1 "register_operand")]
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"TARGET_SSE"
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{
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rtx vec_res = gen_reg_rtx (V4SFmode);
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if (TARGET_SSE3)
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{
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rtx tmp = gen_reg_rtx (V4SFmode);
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emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1]));
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emit_insn (gen_sse3_haddv4sf3 (vec_res, tmp, tmp));
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}
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else
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ix86_expand_reduc (gen_addv4sf3, vec_res, operands[1]);
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emit_insn (gen_vec_extractv4sfsf (operands[0], vec_res, const0_rtx));
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rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
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rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_add<ssehalfvecmodelower>3
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(tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
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emit_insn (gen_reduc_plus_scal_<ssehalfvecmodelower> (operands[0], tmp2));
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DONE;
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})
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;; Modes handled by reduc_sm{in,ax}* patterns.
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(define_mode_iterator REDUC_SSE_SMINMAX_MODE
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[(V4SF "TARGET_SSE") (V2DF "TARGET_SSE")
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(V2DI "TARGET_SSE") (V4SI "TARGET_SSE") (V8HI "TARGET_SSE")
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(V16QI "TARGET_SSE")])
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(define_expand "reduc_<code>_scal_<mode>"
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[(smaxmin:REDUC_SSE_SMINMAX_MODE
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(match_operand:<ssescalarmode> 0 "register_operand")
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(match_operand:REDUC_SSE_SMINMAX_MODE 1 "register_operand"))]
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""
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{
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rtx tmp = gen_reg_rtx (<MODE>mode);
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ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
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emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
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const0_rtx));
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DONE;
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})
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(define_mode_iterator REDUC_SMINMAX_MODE
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[(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")
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(V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")
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(V8SF "TARGET_AVX") (V4DF "TARGET_AVX")
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(V4SF "TARGET_SSE") (V64QI "TARGET_AVX512BW")
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(V64QI "TARGET_AVX512BW")
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(V32HI "TARGET_AVX512BW") (V16SI "TARGET_AVX512F")
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(V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")
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(V8DF "TARGET_AVX512F")])
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(match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))]
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""
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{
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rtx tmp = gen_reg_rtx (<MODE>mode);
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ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
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emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
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const0_rtx));
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rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
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rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_<code><ssehalfvecmodelower>3
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(tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
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emit_insn (gen_reduc_<code>_scal_<ssehalfvecmodelower> (operands[0], tmp2));
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DONE;
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})
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(match_operand:VI_AVX512BW 1 "register_operand"))]
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"TARGET_AVX512F"
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{
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rtx tmp = gen_reg_rtx (<MODE>mode);
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ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
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emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
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const0_rtx));
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rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
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rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_<code><ssehalfvecmodelower>3
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(tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
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emit_insn (gen_reduc_<code>_scal_<ssehalfvecmodelower> (operands[0], tmp2));
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DONE;
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})
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(match_operand:VI_256 1 "register_operand"))]
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"TARGET_AVX2"
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{
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rtx tmp = gen_reg_rtx (<MODE>mode);
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ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
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emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
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const0_rtx));
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rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
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rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
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emit_insn (gen_<code><ssehalfvecmodelower>3
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(tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
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rtx tmp3 = gen_reg_rtx (<ssehalfvecmode>mode);
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ix86_expand_reduc (gen_<code><ssehalfvecmodelower>3, tmp3, tmp2);
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emit_insn (gen_vec_extract<ssehalfvecmodelower><ssescalarmodelower>
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(operands[0], tmp3, const0_rtx));
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DONE;
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})
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