alpha.md (*): Use nonimmediate not general_operand for SET_DEST.
* alpha.md (*): Use nonimmediate not general_operand for SET_DEST. (ffsdi2, extxl, insxh, mskxh): Add missing DImode to SET_SRC. (call-value patterns): Move to end of file. (*): Remove mode from label_ref in (pc) context. (movstrqi): Use memory not general_operand for BLKmode operands. (prologue_stack_probe_loop, builtin_longjmp): Add missing mode to register_operand operands. (peep2 patterns): Convert from commented-out peephole patterns. From-SVN: r29739
This commit is contained in:
parent
2b76013c9a
commit
6ce41093cc
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@ -1,3 +1,14 @@
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Thu Sep 30 17:39:16 1999 Richard Henderson <rth@cygnus.com>
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* alpha.md (*): Use nonimmediate not general_operand for SET_DEST.
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(ffsdi2, extxl, insxh, mskxh): Add missing DImode to SET_SRC.
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(call-value patterns): Move to end of file.
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(*): Remove mode from label_ref in (pc) context.
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(movstrqi): Use memory not general_operand for BLKmode operands.
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(prologue_stack_probe_loop, builtin_longjmp): Add missing mode
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to register_operand operands.
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(peep2 patterns): Convert from commented-out peephole patterns.
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Thu Sep 30 14:39:17 1999 Bernd Schmidt <bernds@cygnus.co.uk>
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* tree.h (enum built_in_function): Rename BUILT_IN_DWARF_REG_SIZE
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@ -901,7 +901,7 @@
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(sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:SI 0 "general_operand" "")
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(set (match_operand:SI 0 "nonimmediate_operand" "")
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(subreg:SI (reg:DI 27) 0))]
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"!TARGET_OPEN_VMS"
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"")
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@ -915,7 +915,7 @@
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(sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:SI 0 "general_operand" "")
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(set (match_operand:SI 0 "nonimmediate_operand" "")
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(subreg:SI (reg:DI 27) 0))]
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"!TARGET_OPEN_VMS"
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"")
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@ -929,7 +929,7 @@
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(sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:SI 0 "general_operand" "")
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(set (match_operand:SI 0 "nonimmediate_operand" "")
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(subreg:SI (reg:DI 27) 0))]
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"!TARGET_OPEN_VMS"
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"")
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@ -943,7 +943,7 @@
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(sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:SI 0 "general_operand" "")
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(set (match_operand:SI 0 "nonimmediate_operand" "")
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(subreg:SI (reg:DI 27) 0))]
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"!TARGET_OPEN_VMS"
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"")
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@ -956,7 +956,7 @@
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(reg:DI 25)))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:DI 0 "general_operand" "")
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(set (match_operand:DI 0 "nonimmediate_operand" "")
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(reg:DI 27))]
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"!TARGET_OPEN_VMS"
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"")
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@ -969,7 +969,7 @@
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(reg:DI 25)))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:DI 0 "general_operand" "")
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(set (match_operand:DI 0 "nonimmediate_operand" "")
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(reg:DI 27))]
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"!TARGET_OPEN_VMS"
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"")
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@ -982,7 +982,7 @@
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(reg:DI 25)))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:DI 0 "general_operand" "")
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(set (match_operand:DI 0 "nonimmediate_operand" "")
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(reg:DI 27))]
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"!TARGET_OPEN_VMS"
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"")
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@ -995,7 +995,7 @@
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(reg:DI 25)))
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(clobber (reg:DI 23))
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(clobber (reg:DI 28))])
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(set (match_operand:DI 0 "general_operand" "")
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(set (match_operand:DI 0 "nonimmediate_operand" "")
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(reg:DI 27))]
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"!TARGET_OPEN_VMS"
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"")
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@ -1233,7 +1233,7 @@
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(define_expand "ffsdi2"
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[(set (match_dup 2)
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(unspec [(match_operand:DI 1 "register_operand" "")] 1))
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(unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
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(set (match_dup 3)
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(plus:DI (match_dup 2) (const_int 1)))
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(set (match_operand:DI 0 "register_operand" "")
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@ -1248,7 +1248,7 @@
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
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(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
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"TARGET_CIX"
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"cttz %1,%0"
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; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
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@ -1582,7 +1582,7 @@
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(and (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
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(and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
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(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
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(const_int 3)))
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(match_operand:DI 3 "mode_mask_operand" "n")))]
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@ -1769,7 +1769,7 @@
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(define_insn "insxh"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec [(match_operand:DI 1 "register_operand" "r")
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(unspec:DI [(match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "mode_width_operand" "n")
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(match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
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""
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@ -1795,7 +1795,7 @@
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(define_insn "mskxh"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec [(match_operand:DI 1 "register_operand" "r")
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(unspec:DI [(match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "mode_width_operand" "n")
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(match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
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""
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@ -3745,7 +3745,7 @@
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(define_insn ""
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[(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
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(match_operand 1 "" ""))
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(use (match_operand:DI 2 "general_operand" "r,m"))
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(use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
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(use (reg:DI 25))
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(use (reg:DI 26))
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(clobber (reg:DI 27))]
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@ -3756,48 +3756,6 @@
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[(set_attr "type" "jsr")
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(set_attr "length" "12,16")])
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(define_insn ""
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[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
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(match_operand 2 "" "")))
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(clobber (reg:DI 27))
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(clobber (reg:DI 26))]
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"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
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"@
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jsr $26,($27),0\;ldgp $29,0($26)
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bsr $26,$%1..ng
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jsr $26,%1\;ldgp $29,0($26)"
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[(set_attr "type" "jsr")
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(set_attr "length" "12,*,16")])
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(define_insn ""
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[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
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(match_operand 2 "" "")))
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(clobber (reg:DI 26))]
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"TARGET_WINDOWS_NT"
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"@
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jsr $26,(%1)
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bsr $26,%1
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jsr $26,%1"
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[(set_attr "type" "jsr")
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(set_attr "length" "*,*,12")])
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(define_insn ""
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[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
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(match_operand 2 "" "")))
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(use (match_operand:DI 3 "general_operand" "r,m"))
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(use (reg:DI 25))
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(use (reg:DI 26))
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(clobber (reg:DI 27))]
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"TARGET_OPEN_VMS"
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"@
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mov %3,$27\;jsr $26,0\;ldq $27,0($29)
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ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
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[(set_attr "type" "jsr")
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(set_attr "length" "12,16")])
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;; Call subroutine returning any type.
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(define_expand "untyped_call"
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@ -3885,7 +3843,7 @@
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(sign_extend:DI (match_operand:SI 0 "register_operand" "")))
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(parallel [(set (pc)
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(plus:DI (match_dup 3)
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(label_ref:DI (match_operand 1 "" ""))))
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(label_ref (match_operand 1 "" ""))))
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(clobber (match_scratch:DI 2 "=r"))])]
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""
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"
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@ -3911,15 +3869,15 @@
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(match_operand:DI 0 "register_operand" ""))
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(set (pc)
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(plus:DI (match_dup 2)
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(label_ref:DI (match_operand 1 "" ""))))]
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(label_ref (match_operand 1 "" ""))))]
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""
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"
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{ operands[2] = gen_reg_rtx (DImode); }")
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(define_insn ""
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[(set (pc)
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(plus:DI (match_operand:DI 0 "register_operand" "r")
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(label_ref:DI (match_operand 1 "" ""))))
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(plus (match_operand:DI 0 "register_operand" "r")
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(label_ref (match_operand 1 "" ""))))
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(clobber (match_scratch:DI 2 "=r"))]
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"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
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&& GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
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@ -4011,7 +3969,7 @@
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(define_insn ""
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[(set (pc)
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(plus:DI (match_operand 0 "register_operand" "r")
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(plus (match_operand:DI 0 "register_operand" "r")
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(label_ref (match_operand 1 "" ""))))]
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"TARGET_OPEN_VMS"
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"jmp $31,(%0),0"
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@ -4225,7 +4183,7 @@
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;; constants.
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(define_expand "movsi"
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[(set (match_operand:SI 0 "general_operand" "")
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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""
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"
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@ -4265,7 +4223,7 @@
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}")
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(define_insn ""
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[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,Q")
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(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
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"! TARGET_FIX
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&& (register_operand (operands[0], DImode)
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@ -4283,7 +4241,7 @@
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[(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
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(define_insn ""
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[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
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(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
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"TARGET_FIX
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&& (register_operand (operands[0], DImode)
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@ -4306,7 +4264,7 @@
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;; memory, and construct long 32-bit constants.
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(define_expand "movdi"
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[(set (match_operand:DI 0 "general_operand" "")
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(match_operand:DI 1 "general_operand" ""))]
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""
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"
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@ -4529,7 +4487,7 @@
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;; registers for reload.
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand" "")
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[(set (match_operand:QI 0 "nonimmediate_operand" "")
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(match_operand:QI 1 "general_operand" ""))]
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""
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"
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@ -4647,7 +4605,7 @@
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}")
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand" "")
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[(set (match_operand:HI 0 "nonimmediate_operand" "")
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(match_operand:HI 1 "general_operand" ""))]
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""
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"
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@ -5043,7 +5001,7 @@
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(define_expand "extzv"
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extract:DI (match_operand:DI 1 "general_operand" "")
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(zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
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(match_operand:DI 2 "immediate_operand" "")
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(match_operand:DI 3 "immediate_operand" "")))]
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""
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@ -5105,8 +5063,8 @@
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;; Argument 3 is the alignment
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(define_expand "movstrqi"
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[(parallel [(set (match_operand:BLK 0 "general_operand" "")
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(match_operand:BLK 1 "general_operand" ""))
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[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
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(match_operand:BLK 1 "memory_operand" ""))
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(use (match_operand:DI 2 "immediate_operand" ""))
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(use (match_operand:DI 3 "immediate_operand" ""))])]
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""
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|
@ -5119,7 +5077,7 @@
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}")
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(define_expand "clrstrqi"
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[(parallel [(set (match_operand:BLK 0 "general_operand" "")
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[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
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(const_int 0))
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(use (match_operand:DI 1 "immediate_operand" ""))
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(use (match_operand:DI 2 "immediate_operand" ""))])]
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|
@ -5228,8 +5186,8 @@
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;; the loop in this one insn.
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(define_insn "prologue_stack_probe_loop"
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[(unspec_volatile [(match_operand 0 "register_operand" "r")
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(match_operand 1 "register_operand" "r")] 5)]
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[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
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(match_operand:DI 1 "register_operand" "r")] 5)]
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""
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"*
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{
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|
@ -5286,7 +5244,7 @@
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"lda %0,%1(%0)")
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(define_expand "builtin_longjmp"
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[(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
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[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
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"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
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"
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{
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|
@ -5397,28 +5355,77 @@
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[(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
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""
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".align %0 #realign")
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;; The call patterns are at the end of the file because their
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;; wildcard operand0 interferes with nice recognition.
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(define_insn ""
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[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
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(match_operand 2 "" "")))
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(clobber (reg:DI 27))
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(clobber (reg:DI 26))]
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"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
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"@
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jsr $26,($27),0\;ldgp $29,0($26)
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bsr $26,$%1..ng
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jsr $26,%1\;ldgp $29,0($26)"
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[(set_attr "type" "jsr")
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(set_attr "length" "12,*,16")])
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|
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(define_insn ""
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||||
[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
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(match_operand 2 "" "")))
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(clobber (reg:DI 26))]
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"TARGET_WINDOWS_NT"
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||||
"@
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jsr $26,(%1)
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bsr $26,%1
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jsr $26,%1"
|
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[(set_attr "type" "jsr")
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||||
(set_attr "length" "*,*,12")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
|
||||
(match_operand 2 "" "")))
|
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(use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
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||||
(use (reg:DI 25))
|
||||
(use (reg:DI 26))
|
||||
(clobber (reg:DI 27))]
|
||||
"TARGET_OPEN_VMS"
|
||||
"@
|
||||
mov %3,$27\;jsr $26,0\;ldq $27,0($29)
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ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
|
||||
[(set_attr "type" "jsr")
|
||||
(set_attr "length" "12,16")])
|
||||
|
||||
|
||||
;; Peepholes go at the end.
|
||||
|
||||
;; Optimize sign-extension of SImode loads. This shows up in the wake of
|
||||
;; reload when converting fp->int.
|
||||
;;
|
||||
;; ??? What to do now that we actually care about the packing and
|
||||
;; alignment of instructions? Perhaps reload can be enlightened, or
|
||||
;; the peephole pass moved up after reload but before sched2?
|
||||
;
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "register_operand" "=r")
|
||||
; (match_operand:SI 1 "memory_operand" "m"))
|
||||
; (set (match_operand:DI 2 "register_operand" "=r")
|
||||
; (sign_extend:DI (match_dup 0)))]
|
||||
; "dead_or_set_p (insn, operands[0])"
|
||||
; "ldl %2,%1")
|
||||
;
|
||||
;(define_peephole
|
||||
; [(set (match_operand:SI 0 "register_operand" "=r")
|
||||
; (match_operand:SI 1 "hard_fp_register_operand" "f"))
|
||||
; (set (match_operand:DI 2 "register_operand" "=r")
|
||||
; (sign_extend:DI (match_dup 0)))]
|
||||
; "TARGET_FIX && dead_or_set_p (insn, operands[0])"
|
||||
; "ftois %1,%2")
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(match_operand:SI 1 "memory_operand" "m"))
|
||||
(set (match_operand:DI 2 "register_operand" "=r")
|
||||
(sign_extend:DI (match_dup 0)))]
|
||||
"rtx_equal_p (operands[0], operands[2])
|
||||
|| reg_dead_p (insn, operands[0])"
|
||||
[(set (match_dup 2)
|
||||
(sign_extend:DI (match_dup 1)))]
|
||||
"")
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(match_operand:SI 1 "hard_fp_register_operand" "f"))
|
||||
(set (match_operand:DI 2 "register_operand" "=r")
|
||||
(sign_extend:DI (match_dup 0)))]
|
||||
"TARGET_FIX
|
||||
&& (rtx_equal_p (operands[0], operands[2])
|
||||
|| reg_dead_p (insn, operands[0]))"
|
||||
[(set (match_dup 2)
|
||||
(sign_extend:DI (match_dup 1)))]
|
||||
"")
|
||||
|
|
Loading…
Reference in New Issue