* config/mips/mips.md: Renumber unspecs. Clean up comments.
From-SVN: r70533
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
aba1f3707b
commit
6d4ede5fc2
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@ -1,3 +1,7 @@
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2003-08-18 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.md: Renumber unspecs. Clean up comments.
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2003-08-17 Roger Sayle <roger@eyesopen.com>
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* simplify-rtx.c (associative_constant_p): New function to test
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@ -30,29 +30,29 @@
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[(UNSPEC_LOAD_DF_LOW 0)
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(UNSPEC_LOAD_DF_HIGH 1)
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(UNSPEC_STORE_DF_HIGH 2)
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(UNSPEC_GET_FNADDR 4)
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(UNSPEC_BLOCKAGE 6)
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(UNSPEC_CPRESTORE 8)
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(UNSPEC_EH_RECEIVER 10)
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(UNSPEC_EH_RETURN 11)
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(UNSPEC_CONSTTABLE_QI 12)
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(UNSPEC_CONSTTABLE_HI 13)
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(UNSPEC_CONSTTABLE_SI 14)
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(UNSPEC_CONSTTABLE_DI 15)
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(UNSPEC_CONSTTABLE_SF 16)
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(UNSPEC_CONSTTABLE_DF 17)
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(UNSPEC_ALIGN_2 18)
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(UNSPEC_ALIGN_4 19)
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(UNSPEC_ALIGN_8 20)
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(UNSPEC_HIGH 22)
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(UNSPEC_LWL 23)
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(UNSPEC_LWR 24)
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(UNSPEC_SWL 25)
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(UNSPEC_SWR 26)
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(UNSPEC_LDL 27)
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(UNSPEC_LDR 28)
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(UNSPEC_SDL 29)
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(UNSPEC_SDR 30)
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(UNSPEC_GET_FNADDR 3)
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(UNSPEC_BLOCKAGE 4)
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(UNSPEC_CPRESTORE 5)
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(UNSPEC_EH_RECEIVER 6)
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(UNSPEC_EH_RETURN 7)
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(UNSPEC_CONSTTABLE_QI 8)
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(UNSPEC_CONSTTABLE_HI 9)
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(UNSPEC_CONSTTABLE_SI 10)
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(UNSPEC_CONSTTABLE_DI 11)
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(UNSPEC_CONSTTABLE_SF 12)
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(UNSPEC_CONSTTABLE_DF 13)
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(UNSPEC_ALIGN_2 14)
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(UNSPEC_ALIGN_4 15)
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(UNSPEC_ALIGN_8 16)
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(UNSPEC_HIGH 17)
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(UNSPEC_LWL 18)
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(UNSPEC_LWR 19)
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(UNSPEC_SWL 20)
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(UNSPEC_SWR 21)
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(UNSPEC_LDL 22)
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(UNSPEC_LDR 23)
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(UNSPEC_SDL 24)
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(UNSPEC_SDR 25)
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;; Constants used in relocation unspecs. RELOC_GOT_PAGE and RELOC_GOT_DISP
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;; are really only available for n32 and n64. However, it is convenient
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@ -69,7 +69,6 @@
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(RELOC_LOADGP_HI 108)
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(RELOC_LOADGP_LO 109)])
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;; ....................
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;;
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;; Attributes
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@ -81,10 +80,12 @@
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(define_attr "jal" "unset,direct,indirect"
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(const_string "unset"))
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;; True for multi-instruction jal macros. jal is always a macro
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;; in SVR4 PIC since it includes an instruction to restore $gp.
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;; Direct jals are also macros in NewABI PIC since they load the
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;; target address into $25.
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;; This attribute is YES if the instruction is a jal macro (not a
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;; real jal instruction).
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;;
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;; jal is always a macro in SVR4 PIC since it includes an instruction to
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;; restore $gp. Direct jals are also macros in NewABI PIC since they
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;; load the target address into $25.
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(define_attr "jal_macro" "no,yes"
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(cond [(eq_attr "jal" "direct")
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(symbol_ref "TARGET_ABICALLS != 0")
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@ -129,24 +130,47 @@
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(const_string "unknown")))
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;; Main data type used by the insn
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(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
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(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
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(const_string "unknown"))
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;; Is this an extended instruction in mips16 mode?
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(define_attr "extended_mips16" "no,yes"
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(const_string "no"))
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;; Length (in # of bytes). A conditional branch is allowed only to a
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;; location within a signed 18-bit offset of the delay slot. If that
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;; provides too smal a range, we use the `j' instruction. This
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;; instruction takes a 28-bit value, but that value is not an offset.
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;; Instead, it's bitwise-ored with the high-order four bits of the
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;; instruction in the delay slot, which means it cannot be used to
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;; cross a 256MB boundary. We could fall back back on the jr,
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;; instruction which allows full access to the entire address space,
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;; but we do not do so at present.
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;; Length of instruction in bytes.
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(define_attr "length" ""
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(cond [(eq_attr "type" "branch")
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(cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
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;; If a branch is outside this range, we have a choice of two
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;; sequences. For PIC, an out-of-range branch like:
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;;
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;; bne r1,r2,target
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;; dslot
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;;
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;; becomes the equivalent of:
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;;
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;; beq r1,r2,1f
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;; dslot
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;; la $at,target
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;; jr $at
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;; nop
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;; 1:
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;;
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;; where the load address can be up to three instructions long
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;; (lw, nop, addiu).
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;;
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;; The non-PIC case is similar except that we use a direct
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;; jump instead of an la/jr pair. Since the target of this
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;; jump is an absolute 28-bit bit address (the other bits
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;; coming from the address of the delay slot) this form cannot
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;; cross a 256MB boundary. We could provide the option of
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;; using la/jr in this case too, but we do not do so at
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;; present.
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;;
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;; Note that this value does not account for the delay slot
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;; instruction, whose length is added separately. If the RTL
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;; pattern has no explicit delay slot, mips_adjust_insn_length
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;; will add the length of the implicit nop.
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(eq_attr "type" "branch")
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(cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
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(const_int 131072))
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(const_int 4)
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@ -154,12 +178,14 @@
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(const_int 0))
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(const_int 24)
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] (const_int 12))
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(eq_attr "type" "const")
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(symbol_ref "mips_const_insns (operands[1]) * 4")
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(eq_attr "type" "load")
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(symbol_ref "mips_fetch_insns (operands[1]) * 4")
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(eq_attr "type" "store")
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(symbol_ref "mips_fetch_insns (operands[0]) * 4")
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;; In the worst case, a call macro will take 8 instructions:
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;;
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;; lui $25,%call_hi(FOO)
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@ -172,9 +198,11 @@
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;; nop
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(eq_attr "jal_macro" "yes")
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(const_int 32)
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(and (eq_attr "extended_mips16" "yes")
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(ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
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(const_int 8)
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(and (eq_attr "type" "idiv")
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(ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0)))
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(cond [(ne (symbol_ref "TARGET_MIPS16") (const_int 0))
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@ -184,16 +212,6 @@
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;; Attribute describing the processor. This attribute must match exactly
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;; with the processor_type enumeration in mips.h.
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;; Attribute describing the processor
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;; (define_attr "cpu" "default,r3000,r6000,r4000"
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;; (const
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;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
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;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
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;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
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;; (const_string "default"))))
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;; ??? Fix everything that tests this attribute.
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(define_attr "cpu"
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"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
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(const (symbol_ref "mips_tune")))
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@ -239,23 +257,19 @@
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(const_string "no")))
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;; Attribute defining whether or not we can use the branch-likely instructions
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(define_attr "branch_likely" "no,yes"
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(const
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(if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
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(const_string "yes")
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(const_string "no"))))
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;; Describe a user's asm statement.
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(define_asm_attributes
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[(set_attr "type" "multi")])
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;; .........................
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;;
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;; Delay slots, can't describe load/fcmp/xfer delay slots here
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;; Branch, call and jump delay slots
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;;
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;; .........................
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@ -276,9 +290,7 @@
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[(eq_attr "can_delay" "yes")
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(nil)
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(nil)])
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;; .........................
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;;
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;; Functional units
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@ -593,32 +605,6 @@
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
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58 58)
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;; The following functional units do not use the cpu type, and use
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;; much less memory in genattrtab.c.
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;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
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;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
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;;
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;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
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;;
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;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
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;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
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;;
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;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
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;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
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;;
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;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
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;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
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;;
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;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
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;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
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;;
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;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
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;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
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;;
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;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
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;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
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;; Include scheduling descriptions.
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(include "5400.md")
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@ -626,8 +612,7 @@
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(include "7000.md")
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(include "9000.md")
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(include "sr71k.md")
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;;
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;; ....................
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;;
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@ -661,10 +646,6 @@
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DONE;
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}")
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;; Match a TRAP_IF with 2nd arg of 0. The div_trap_* insns match a
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;; 2nd arg of any CONST_INT, so this insn must appear first.
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;; gen_div_trap always generates TRAP_IF with 2nd arg of 6 or 7.
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(define_insn ""
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[(trap_if (match_operator 0 "trap_cmp_op"
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[(match_operand:SI 1 "reg_or_0_operand" "d")
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@ -1224,7 +1205,6 @@
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(const_int 4)
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(const_int 8))
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(const_int 4)])])
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;;
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;; ....................
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@ -2504,6 +2484,7 @@
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{ return mips_output_division ("ddivu\\t$0,%1,%2", operands); }
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[(set_attr "type" "idiv")
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(set_attr "mode" "DI")])
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;;
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;; ....................
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;;
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@ -2544,7 +2525,6 @@
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"rsqrt.s\\t%0,%2"
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[(set_attr "type" "frsqrt")
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(set_attr "mode" "SF")])
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;;
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;; ....................
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@ -2616,7 +2596,6 @@
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"abs.s\\t%0,%1"
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[(set_attr "type" "fabs")
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(set_attr "mode" "SF")])
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;;
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;; ....................
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@ -2693,9 +2672,7 @@ move\\t%0,%z4\\n\\
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[(set_attr "type" "multi")
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(set_attr "mode" "DI")
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(set_attr "length" "28")])
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;;
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;; ...................
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;;
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@ -2719,7 +2696,7 @@ move\\t%0,%z4\\n\\
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"dclz\\t%0,%1"
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[(set_attr "type" "arith")
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(set_attr "mode" "DI")])
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;;
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;; ....................
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;;
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@ -2834,7 +2811,7 @@ move\\t%0,%z4\\n\\
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;; ....................
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;;
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;; Many of these instructions uses trivial define_expands, because we
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;; Many of these instructions use trivial define_expands, because we
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;; want to use a different set of constraints when TARGET_MIPS16.
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(define_expand "andsi3"
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@ -3216,7 +3193,6 @@ move\\t%0,%z4\\n\\
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"andi\\t%0,%1,0xff"
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[(set_attr "type" "darith")
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(set_attr "mode" "HI")])
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;;
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;; ....................
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@ -3657,9 +3633,7 @@ move\\t%0,%z4\\n\\
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"cvt.d.s\\t%0,%1"
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[(set_attr "type" "fcvt")
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(set_attr "mode" "DF")])
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;;
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;; ....................
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;;
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@ -3737,14 +3711,6 @@ move\\t%0,%z4\\n\\
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(set_attr "mode" "DF")
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(set_attr "length" "36")])
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;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
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;;; but not in the chapter that describes the FPU. It is not mentioned at all
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;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
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;;; Deleting this means that we now need two libgcc2.a libraries. One for
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;;; the 32 bit calling convention and one for the 64 bit calling convention.
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;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
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(define_insn "fix_truncdfdi2"
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[(set (match_operand:DI 0 "register_operand" "=f")
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@ -3756,9 +3722,6 @@ move\\t%0,%z4\\n\\
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(set_attr "length" "4")])
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;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
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;;; but not in the chapter that describes the FPU. It is not mentioned at all
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;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
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(define_insn "fix_truncsfdi2"
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[(set (match_operand:DI 0 "register_operand" "=f")
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(fix:DI (match_operand:SF 1 "register_operand" "f")))]
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@ -3991,7 +3954,6 @@ move\\t%0,%z4\\n\\
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DONE;
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}
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}")
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;;
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;; ....................
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@ -4659,7 +4621,7 @@ move\\t%0,%z4\\n\\
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;; Unlike most other insns, the move insns can't be split with
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;; different predicates, because register spilling and other parts of
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;; the compiler, have memoized the insn number already.
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;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
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;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
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(define_expand "movhi"
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[(set (match_operand:HI 0 "nonimmediate_operand" "")
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@ -4680,9 +4642,6 @@ move\\t%0,%z4\\n\\
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}
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}")
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;; The difference between these two is whether or not ints are allowed
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;; in FP registers (off by default, use -mdebugh to enable).
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(define_insn "movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
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(match_operand:HI 1 "general_operand" "d,IK,m,dJ,*f,*d,*f,*d,*x"))]
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|
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@ -4784,7 +4743,7 @@ move\\t%0,%z4\\n\\
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;; Unlike most other insns, the move insns can't be split with
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;; different predicates, because register spilling and other parts of
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;; the compiler, have memoized the insn number already.
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;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
|
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;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
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|
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(define_expand "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "")
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@ -4805,9 +4764,6 @@ move\\t%0,%z4\\n\\
|
|||
}
|
||||
}")
|
||||
|
||||
;; The difference between these two is whether or not ints are allowed
|
||||
;; in FP registers (off by default, use -mdebugh to enable).
|
||||
|
||||
(define_insn "movqi_internal"
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
|
||||
(match_operand:QI 1 "general_operand" "d,IK,m,dJ,*f,*d,*f,*d,*x"))]
|
||||
|
|
@ -5105,7 +5061,7 @@ move\\t%0,%z4\\n\\
|
|||
;;
|
||||
;; ....................
|
||||
|
||||
;; Many of these instructions uses trivial define_expands, because we
|
||||
;; Many of these instructions use trivial define_expands, because we
|
||||
;; want to use a different set of constraints when TARGET_MIPS16.
|
||||
|
||||
(define_expand "ashlsi3"
|
||||
|
|
@ -6257,7 +6213,6 @@ move\\t%0,%z4\\n\\
|
|||
{
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
|
||||
}")
|
||||
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
|
|
@ -6277,7 +6232,7 @@ move\\t%0,%z4\\n\\
|
|||
;; Different CC modes are used, based on what type of branch is
|
||||
;; done, so that we can constrain things appropriately. There
|
||||
;; are assumptions in the rest of GCC that break if we fold the
|
||||
;; operands into the branchs for integer operations, and use cc0
|
||||
;; operands into the branches for integer operations, and use cc0
|
||||
;; for floating point, so we use the fp status register instead.
|
||||
;; If needed, an appropriate temporary is created to hold the
|
||||
;; of the integer compare.
|
||||
|
|
@ -6375,7 +6330,6 @@ move\\t%0,%z4\\n\\
|
|||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
|
|
@ -6939,7 +6893,6 @@ move\\t%0,%z4\\n\\
|
|||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
|
|
@ -7826,7 +7779,6 @@ move\\t%0,%z4\\n\\
|
|||
(xor:DI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"")
|
||||
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
|
|
@ -7996,7 +7948,6 @@ move\\t%0,%z4\\n\\
|
|||
"c.le.s\t%Z0%2,%1"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
|
|
@ -8292,8 +8243,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
|||
DONE;
|
||||
})
|
||||
|
||||
;; Restore the gp that we saved above. Despite the comment, it seems that
|
||||
;; older code did recalculate the gp from $25. Continue to jump through
|
||||
;; Restore the gp that we saved above. Despite the earlier comment, it seems
|
||||
;; that older code did recalculate the gp from $25. Continue to jump through
|
||||
;; $25 for compatibility (we lose nothing by doing so).
|
||||
|
||||
(define_expand "builtin_longjmp"
|
||||
|
|
@ -8375,7 +8326,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
|||
})
|
||||
|
||||
;; Trivial return. Make it look like a normal return insn as that
|
||||
;; allows jump optimizations to work better .
|
||||
;; allows jump optimizations to work better.
|
||||
|
||||
(define_insn "return"
|
||||
[(return)]
|
||||
"mips_can_use_return_insn ()"
|
||||
|
|
@ -8466,11 +8418,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
|||
;;
|
||||
;; ....................
|
||||
|
||||
;; Sibling calls. All these patterns use direct jumps.
|
||||
;; Sibling calls. All these patterns use jump instructions.
|
||||
|
||||
;; call_insn_operand will only accepts constant addresses if a direct
|
||||
;; jump is acceptable. Since the 'S' constraint is defined in terms of
|
||||
;; call_insn_operand, the same is true of the constraints.
|
||||
;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
|
||||
;; addresses if a direct jump is acceptable. Since the 'S' constraint
|
||||
;; is defined in terms of call_insn_operand, the same is true of the
|
||||
;; constraints.
|
||||
|
||||
;; When we use an indirect jump, we need a register that will be
|
||||
;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
|
||||
|
|
@ -8737,24 +8690,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
|||
return "#nop";
|
||||
}
|
||||
[(set_attr "type" "arith")])
|
||||
|
||||
;; The MIPS chip does not seem to require stack probes.
|
||||
;;
|
||||
;; (define_expand "probe"
|
||||
;; [(set (match_dup 0)
|
||||
;; (match_dup 1))]
|
||||
;; ""
|
||||
;; "
|
||||
;; {
|
||||
;; operands[0] = gen_reg_rtx (SImode);
|
||||
;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
|
||||
;; MEM_VOLATILE_P (operands[1]) = TRUE;
|
||||
;;
|
||||
;; /* fall through and generate default code */
|
||||
;; }")
|
||||
;;
|
||||
|
||||
;;
|
||||
;; MIPS4 Conditional move instructions.
|
||||
|
||||
(define_insn ""
|
||||
|
|
|
|||
Loading…
Reference in New Issue