parent
7d4d4d22e4
commit
6d51800282
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@ -63,7 +63,7 @@
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;; # instructions (4 bytes each)
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(define_attr "length" "" (const_int 1))
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;; whether or not an instruction has a mandiatory delay slot
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;; whether or not an instruction has a mandatory delay slot
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(define_attr "dslot" "no,yes"
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(if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp")
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(const_string "yes")
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@ -71,21 +71,21 @@
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;; Attribute describing the processor
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(define_attr "cpu" "default,r3000,r4000,r6000"
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; (const
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(const
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(cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_DEFAULT")) (const_string "default")
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(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
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(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
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(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
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(const_string "default")))
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(const_string "default"))))
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;; Attribute defining whether or not we can use the branch-likely instructions
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;; (MIPS ISA level 2)
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(define_attr "branch_likely" "no,yes"
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; (const
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(const
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(if_then_else (ge (symbol_ref "mips_isa") (const_int 2))
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(const_string "yes")
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(const_string "no")))
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(const_string "no"))))
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;; Describe a user's asm statement.
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@ -491,8 +491,8 @@
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&& GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
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[(set (match_dup 3)
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(lt:CC (subreg:SI (match_dup 1) 0)
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(subreg:SI (match_dup 2) 0)))
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(ltu:CC (subreg:SI (match_dup 1) 0)
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(subreg:SI (match_dup 2) 0)))
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(set (subreg:SI (match_dup 0) 0)
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(minus:SI (subreg:SI (match_dup 1) 0)
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@ -518,8 +518,8 @@
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&& GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
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[(set (match_dup 3)
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(lt:CC (subreg:SI (match_dup 1) 1)
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(subreg:SI (match_dup 2) 1)))
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(ltu:CC (subreg:SI (match_dup 1) 1)
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(subreg:SI (match_dup 2) 1)))
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(set (subreg:SI (match_dup 0) 1)
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(minus:SI (subreg:SI (match_dup 1) 1)
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@ -1617,14 +1617,10 @@ move\\t%0,%z4\\n\\
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;; ....................
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;; unaligned word moves generated by the block moves.
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;; We use (use (reg:SI 0)) to select this pattern rather than the
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;; normal movsi. Make these before the normal move patterns so they
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;; match first.
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(define_expand "movsi_unaligned"
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[(parallel [(set (match_operand:SI 0 "general_operand" "")
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(match_operand:SI 1 "general_operand" ""))
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(use (reg:SI 0))])]
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[(set (match_operand:SI 0 "general_operand" "")
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(unspec [(match_operand:SI 1 "general_operand" "")] 0))]
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""
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"
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{
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@ -1653,15 +1649,14 @@ move\\t%0,%z4\\n\\
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(define_insn "movsi_ulw"
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[(set (match_operand:SI 0 "register_operand" "=&d,&d,d,d")
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(match_operand:SI 1 "general_operand" "R,o,dIKL,M"))
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(use (reg:SI 0))]
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(unspec [(match_operand:SI 1 "general_operand" "R,o,dIKL,M")] 0))]
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""
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"*
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{
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extern rtx eliminate_constant_term ();
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enum rtx_code code;
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char *ret;
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int offset;
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rtx offset;
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rtx addr;
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rtx mem_addr;
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@ -1674,11 +1669,11 @@ move\\t%0,%z4\\n\\
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/* The stack/frame pointers are always aligned, so we can convert
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to the faster lw if we are referencing an aligned stack location. */
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offset = 0;
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offset = const0_rtx;
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addr = XEXP (operands[1], 0);
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mem_addr = eliminate_constant_term (addr, &offset);
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if ((offset & (UNITS_PER_WORD-1)) == 0
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if ((INTVAL (offset) & (UNITS_PER_WORD-1)) == 0
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&& (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
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ret = \"lw\\t%0,%1\";
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@ -1705,13 +1700,12 @@ move\\t%0,%z4\\n\\
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(define_insn "movsi_usw"
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[(set (match_operand:SI 0 "memory_operand" "=R,o")
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(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ"))
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(use (reg:SI 0))]
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(unspec [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 0))]
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""
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"*
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{
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extern rtx eliminate_constant_term ();
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int offset = 0;
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rtx offset = const0_rtx;
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rtx addr = XEXP (operands[0], 0);
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rtx mem_addr = eliminate_constant_term (addr, &offset);
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/* The stack/frame pointers are always aligned, so we can convert
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to the faster sw if we are referencing an aligned stack location. */
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if ((offset & (UNITS_PER_WORD-1)) == 0
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if ((INTVAL (offset) & (UNITS_PER_WORD-1)) == 0
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&& (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
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return \"sw\\t%1,%0\";
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;; the compiler, have memoized the insn number already.
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(define_insn "movdi"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*f,*f,*f,*f,*R,*o,*d,*x")
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(match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*f,*d,*f,*R,*o,*f,*f,*x,*d"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*x")
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(match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*x,*d"))]
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""
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"* return mips_move_2words (operands, insn); "
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[(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo")
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(set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,DI,DI,DI,DI,DI,DI,DI,DI")
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(set_attr "length" "2,4,2,4,2,4,2,2,1,2,4,2,4,2,2")])
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[(set_attr "type" "move,arith,load,load,store,store,hilo,hilo")
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(set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,DI")
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(set_attr "length" "2,4,2,4,2,4,2,2")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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case NE: return \"%*bne%?\\t%z2,%.,%1\";
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case GTU: return \"%*bne%?\\t%z2,%.,%1\";
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case LEU: return \"%*beq%?\\t%z2,%.,%1\";
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case GEU: return \"%*j\\t%1\";
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case LTU: return \"#%*bltuz\\t%z2,%1\";
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}
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return \"%*b%C0z%?\\t%z2,%1\";
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case NE: return \"%*beq%?\\t%z2,%.,%1\";
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case GTU: return \"%*beq%?\\t%z2,%.,%1\";
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case LEU: return \"%*bne\\t%z2,%.,%1\";
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case GEU: return \"#%*bgeuz\\t%z2,%1\";
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case LTU: return \"%*j\\t%1\";
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}
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return \"%*b%N0z%?\\t%z2,%1\";
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