2012-02-25 Catherine Moore <clm@codesourcery.com>
Revert microMIPS patch. From-SVN: r196259
This commit is contained in:
Catherine Moore
parent
5e5df392f8
commit
6d65e8f1fc
129
gcc/ChangeLog
129
gcc/ChangeLog
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@ -1,3 +1,132 @@
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2013-02-25 Catherine Moore <clm@codesourcery.com>
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Revert:
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2013-02-24 Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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Tom de Vries <tom@codesourcery.com>
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Nathan Sidwell <nathan@codesourcery.com>
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Iain Sandoe <iain@codesourcery.com>
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Nathan Froyd <froydnj@codesourcery.com>
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Chao-ying Fu <fu@mips.com>
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* doc/extend.texi: (micromips, nomicromips, nocompression):
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Document new function attributes.
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* doc/invoke.texi (minterlink-compressed, mmicromips,
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m14k, m14ke, m14kec): Document new options.
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(minterlink-mips16): Update documentation.
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* doc/md.texi (ZC, ZD): Document new constraints.
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* configure.ac (gcc_cv_as_micromips): Check if linker
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supports the .set micromips directive.
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* configure: Regenerate.
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* config.in: Regenerate.
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* config/mips/mips-tables.opt: Regenerate.
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* config/mips/micromips.md: New file.
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* constraints.md (ZC, AD): New constraints.
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* config/mips/predicates.md (movep_src_register): New predicate.
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(movep_src_operand): New predicate.
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(non_volatile_mem_operand): New predicate.
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* config/mips/mips.md (multimem): New type.
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(length): Differentiate between 17-bit and 18-bit branch offsets.
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(MOVEP1, MOVEP2): New mode iterator.
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(mov_<load>l): Use ZC constraint.
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(mov_<load>r): Likewise.
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(mov_<store>l): Likewise.
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(mov_<store>r): Likewise.
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(*branch_equality<mode>_inverted): Add microMIPS support.
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(*branch_equality<mode>): Likewise.
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(*jump_absolute): Likewise.
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(indirect_jump_<mode>): Likewise.
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(tablejump_<mode>): Likewise.
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(<optab>_internal): Likewise.
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(sibcall_internal): Likewise.
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(sibcall_value_internal): Likewise.
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(prefetch): Use constraint ZD.
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* config/mips/mips.opt (minterlink-compressed): New option.
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(minterlink-mips16): Now an alias for minterlink-compressed.
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(mmicromips): New option.
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* config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint.
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(compare_and_swap_12): Likewise.
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(sync_add<mode>): Likewise.
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(sync_<optab>_12): Likewise.
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(sync_old_<optab>_12): Likewise.
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(sync_new_<optab>_12): Likewise.
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(sync_nand_12): Likewise.
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(sync_old_nand_12): Likewise.
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(sync_new_nand_12): Likewise.
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(sync_sub<mode>): Likewise.
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(sync_old_add<mode>): Likewise.
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(sync_old_sub<mode>): Likewise.
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(sync_new_add<mode>): Likewise.
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(sync_new_sub<mode>): Likewise.
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(sync_<optab><mode>): Likewise.
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(sync_old_<optab><mode>): Likewise.
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(sync_new_<optab><mode>): Likewise.
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(sync_nand<mode>): Likewise.
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(sync_old_nand<mode>): Likewise.
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(sync_new_nand<mode>): Likewise.
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(sync_lock_test_and_set<mode>): Likewise.
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(test_and_set_12): Likewise.
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(atomic_compare_and_swap<mode>): Likewise.
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(atomic_exchange<mode>_llsc): Likewise.
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(atomic_fetch_add<mode>_llsc): Likewise.
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* config/mips/mips-cpus.def (m14kc, m14k): New processors.
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* config/mips/mips-protos.h (umips_output_save_restore): New prototype.
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(umips_save_restore_pattern_p): Likewise.
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(umips_load_store_pair_p): Likewise.
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(umips_output_load_store_pair): Likewise.
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(umips_movep_target_p): Likewise.
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(umips_12bit_offset_address_p): Likewise.
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* config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS.
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(mips_base_mips16): Rename this...
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(mips_base_compression_flags): ...to this. Update all uses.
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(mips_attribute_table): Add micromips, nomicromips and nocompression.
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(mips_mips16_decl_p): Delete.
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(mips_nomips16_decl_p): Delete.
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(mips_get_compress_on_flags): New function.
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(mips_get_compress_off_flags): New function.
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(mips_get_compress_mode): New function.
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(mips_get_compress_on_name): New function.
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(mips_get_compress_off_name): New function.
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(mips_insert_attributes): Support multiple compression types.
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(mips_merge_decl_attributes): Likewise.
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(umips_12bit_offset_address_p): New function.
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(mips_start_function_definition): Emit .set micromips directive.
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(mips_call_may_need_jalx_p): New function.
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(mips_function_ok_for_sibcall): Add microMIPS support.
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(mips_print_operand_punctuation): Support short delay slots and
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compact jumps.
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(umips_swm_mask, umips_swm_encoding): New.
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(umips_build_save_restore): New function.
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(mips_for_each_saved_gpr_and_fpr): Add microMIPS support.
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(was_mips16_p): Remove.
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(old_compression_mode): New.
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(mips_set_compression_mode): New function.
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(mips_set_current_function): Add microMIPS support.
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(mips_option_override): Likewise.
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(umips_save_restore_pattern_p): New function.
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(umips_output_save_restore): New function.
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(umips_load_store_pair_p_1): New function.
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(umips_load_store_pair_p): New function.
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(umips_output_load_store_pair_1): New function.
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(umips_output_load_store_pair): New function.
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(umips_movep_target_p) New function.
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(mips_prepare_pch_save): Add microMIPS support.
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* config/mips/mips.h (TARGET_COMPRESSION): New.
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(TARGET_CPU_CPP_BUILTINS): Update macro
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to use new compression flags and to support microMIPS.
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(MIPS_ISA_LEVEL_SPEC): Add m14k processors.
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(MIPS_ARCH_FLOAT_SPEC): Likewise.
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(ISA_HAS_LWXS): Include TARGET_MICROMIPS.
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(ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS.
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(ASM_SPEC): Support mmicromips and mno-micromips.
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(M16STORE_REG_P): New macro.
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(MIPS_CALL): Support TARGET_MICROMIPS.
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(MICROMIPS_J): New macro.
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(mips_base_mips16): Rename this...
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(mips_base_compression_flags): ...to this.
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(UMIPS_12BIT_OFFSET_P): New macro.
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* config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS.
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(MULTILIB_DIRNAMES): Likewise.
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2013-02-25 Tom de Vries <tom@codesourcery.com>
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PR rtl-optimization/56131
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@ -1034,12 +1034,6 @@
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#endif
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/* Define if your assembler supports the .set micromips directive */
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#ifndef USED_FOR_TARGET
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#undef HAVE_GAS_MICROMIPS
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#endif
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/* Define if your assembler supports .nsubspa comdat option. */
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#ifndef USED_FOR_TARGET
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#undef HAVE_GAS_NSUBSPA_COMDAT
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@ -232,27 +232,6 @@
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"@internal"
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(match_operand 0 "low_bitmask_operand"))
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(define_memory_constraint "ZC"
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"When compiling microMIPS code, this constraint matches a memory operand
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whose address is formed from a base register and a 12-bit offset. These
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operands can be used for microMIPS instructions such as @code{ll} and
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@code{sc}. When not compiling for microMIPS code, @code{ZC} is
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equivalent to @code{R}."
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(and (match_code "mem")
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(if_then_else
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(match_test "TARGET_MICROMIPS")
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(match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
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(match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))
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(define_address_constraint "ZD"
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"When compiling microMIPS code, this constraint matches an address operand
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that is formed from a base register and a 12-bit offset. These operands
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can be used for microMIPS instructions such as @code{prefetch}. When
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not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}."
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(if_then_else (match_test "TARGET_MICROMIPS")
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(match_test "umips_12bit_offset_address_p (op, mode)")
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(match_test "mips_address_insns (op, mode, false)")))
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(define_memory_constraint "ZR"
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"@internal
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An address valid for loading/storing register exclusive"
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@ -1,125 +0,0 @@
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;; Copyright (C) 2013 Free Software Foundation, Inc.
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;;
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;; micromips.md Machine Description for the microMIPS instruction set
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_insn "*store_word_multiple"
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[(match_parallel 0 ""
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[(set (match_operand:SI 1 "memory_operand")
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(match_operand:SI 2 "register_operand"))])]
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"TARGET_MICROMIPS
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&& umips_save_restore_pattern_p (true, operands[0])"
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{ return umips_output_save_restore (true, operands[0]); }
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[(set_attr "type" "multimem")
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(set_attr "mode" "SI")
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(set_attr "can_delay" "no")])
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(define_insn "*load_word_multiple"
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[(match_parallel 0 ""
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[(set (match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "memory_operand"))])]
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"TARGET_MICROMIPS
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&& umips_save_restore_pattern_p (false, operands[0])"
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{ return umips_output_save_restore (false, operands[0]); }
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[(set_attr "type" "multimem")
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(set_attr "mode" "SI")
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(set_attr "can_delay" "no")])
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;; For LWP.
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(define_peephole2
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[(set (match_operand:SI 0 "d_operand" "")
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(match_operand:SI 1 "non_volatile_mem_operand" ""))
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(set (match_operand:SI 2 "d_operand" "")
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(match_operand:SI 3 "non_volatile_mem_operand" ""))]
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"TARGET_MICROMIPS
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&& umips_load_store_pair_p (true, operands)"
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[(parallel [(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (match_dup 3))])])
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;; The behavior of the LWP insn is undefined if placed in a delay slot.
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(define_insn "*lwp"
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[(parallel [(set (match_operand:SI 0 "d_operand")
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(match_operand:SI 1 "non_volatile_mem_operand"))
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(set (match_operand:SI 2 "d_operand")
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(match_operand:SI 3 "non_volatile_mem_operand"))])]
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"TARGET_MICROMIPS
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&& umips_load_store_pair_p (true, operands)"
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{
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umips_output_load_store_pair (true, operands);
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return "";
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}
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[(set_attr "type" "load")
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(set_attr "mode" "SI")
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(set_attr "can_delay" "no")])
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;; For SWP.
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(define_peephole2
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[(set (match_operand:SI 0 "non_volatile_mem_operand" "")
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(match_operand:SI 1 "d_operand" ""))
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(set (match_operand:SI 2 "non_volatile_mem_operand" "")
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(match_operand:SI 3 "d_operand" ""))]
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"TARGET_MICROMIPS
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&& umips_load_store_pair_p (false, operands)"
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[(parallel [(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (match_dup 3))])])
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;; The behavior of the SWP insn is undefined if placed in a delay slot.
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(define_insn "*swp"
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[(parallel [(set (match_operand:SI 0 "non_volatile_mem_operand")
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(match_operand:SI 1 "d_operand"))
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(set (match_operand:SI 2 "non_volatile_mem_operand")
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(match_operand:SI 3 "d_operand"))])]
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"TARGET_MICROMIPS
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&& umips_load_store_pair_p (false, operands)"
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{
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umips_output_load_store_pair (false, operands);
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return "";
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}
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[(set_attr "type" "store")
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(set_attr "mode" "SI")
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(set_attr "can_delay" "no")])
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;; For MOVEP.
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(define_peephole2
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[(set (match_operand:MOVEP1 0 "register_operand" "")
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(match_operand:MOVEP1 1 "movep_src_operand" ""))
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(set (match_operand:MOVEP2 2 "register_operand" "")
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(match_operand:MOVEP2 3 "movep_src_operand" ""))]
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"TARGET_MICROMIPS
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&& umips_movep_target_p (operands[0], operands[2])"
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[(parallel [(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (match_dup 3))])])
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;; The behavior of the MOVEP insn is undefined if placed in a delay slot.
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(define_insn "*movep<MOVEP1:mode><MOVEP2:mode>"
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[(parallel [(set (match_operand:MOVEP1 0 "register_operand")
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(match_operand:MOVEP1 1 "movep_src_operand"))
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(set (match_operand:MOVEP2 2 "register_operand")
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(match_operand:MOVEP2 3 "movep_src_operand"))])]
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"TARGET_MICROMIPS
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&& umips_movep_target_p (operands[0], operands[2])"
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{
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if (REGNO (operands[0]) < REGNO (operands[2]))
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return "movep\t%0,%2,%z1,%z3";
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else
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return "movep\t%2,%0,%z3,%z1";
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}
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[(set_attr "type" "move")
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(set_attr "mode" "<MODE>")
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(set_attr "can_delay" "no")])
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@ -92,8 +92,6 @@ MIPS_CPU ("4ksc", PROCESSOR_4KC, 32, 0)
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/* MIPS32 Release 2 processors. */
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MIPS_CPU ("m4k", PROCESSOR_M4K, 33, 0)
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MIPS_CPU ("m14kc", PROCESSOR_M4K, 33, 0)
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MIPS_CPU ("m14k", PROCESSOR_M4K, 33, 0)
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MIPS_CPU ("4kec", PROCESSOR_4KC, 33, 0)
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MIPS_CPU ("4kem", PROCESSOR_4KC, 33, 0)
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MIPS_CPU ("4kep", PROCESSOR_4KP, 33, 0)
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@ -350,12 +350,6 @@ extern void mips_expand_vec_reduc (rtx, rtx, rtx (*)(rtx, rtx, rtx));
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extern void mips_expand_vec_minmax (rtx, rtx, rtx,
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rtx (*) (rtx, rtx, rtx), bool);
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extern const char *umips_output_save_restore (bool, rtx);
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extern bool umips_save_restore_pattern_p (bool, rtx);
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extern bool umips_load_store_pair_p (bool, rtx *);
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extern void umips_output_load_store_pair (bool, rtx *);
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extern bool umips_movep_target_p (rtx, rtx);
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extern bool umips_12bit_offset_address_p (rtx, enum machine_mode);
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extern rtx mips_expand_thread_pointer (rtx);
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extern bool mips_eh_uses (unsigned int);
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@ -373,260 +373,254 @@ EnumValue
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Enum(mips_arch_opt_value) String(m4k) Value(39) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(m14kc) Value(40) Canonical
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Enum(mips_arch_opt_value) String(4kec) Value(40) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(m14k) Value(41) Canonical
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Enum(mips_arch_opt_value) String(r4kec) Value(40)
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EnumValue
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Enum(mips_arch_opt_value) String(4kec) Value(42) Canonical
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Enum(mips_arch_opt_value) String(4kem) Value(41) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(r4kec) Value(42)
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Enum(mips_arch_opt_value) String(r4kem) Value(41)
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EnumValue
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Enum(mips_arch_opt_value) String(4kem) Value(43) Canonical
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Enum(mips_arch_opt_value) String(4kep) Value(42) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(r4kem) Value(43)
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Enum(mips_arch_opt_value) String(r4kep) Value(42)
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EnumValue
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Enum(mips_arch_opt_value) String(4kep) Value(44) Canonical
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Enum(mips_arch_opt_value) String(4ksd) Value(43) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(r4kep) Value(44)
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Enum(mips_arch_opt_value) String(r4ksd) Value(43)
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EnumValue
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Enum(mips_arch_opt_value) String(4ksd) Value(45) Canonical
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Enum(mips_arch_opt_value) String(24kc) Value(44) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(r4ksd) Value(45)
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Enum(mips_arch_opt_value) String(r24kc) Value(44)
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EnumValue
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Enum(mips_arch_opt_value) String(24kc) Value(46) Canonical
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Enum(mips_arch_opt_value) String(24kf2_1) Value(45) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(r24kc) Value(46)
|
||||
Enum(mips_arch_opt_value) String(r24kf2_1) Value(45)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kf2_1) Value(47) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kf) Value(46) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kf2_1) Value(47)
|
||||
Enum(mips_arch_opt_value) String(r24kf) Value(46)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kf) Value(48) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kf1_1) Value(47) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kf) Value(48)
|
||||
Enum(mips_arch_opt_value) String(r24kf1_1) Value(47)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kf1_1) Value(49) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kfx) Value(48) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kf1_1) Value(49)
|
||||
Enum(mips_arch_opt_value) String(r24kfx) Value(48)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kfx) Value(50) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kx) Value(49) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kfx) Value(50)
|
||||
Enum(mips_arch_opt_value) String(r24kx) Value(49)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kx) Value(51) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kec) Value(50) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kx) Value(51)
|
||||
Enum(mips_arch_opt_value) String(r24kec) Value(50)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kec) Value(52) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kef2_1) Value(51) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kec) Value(52)
|
||||
Enum(mips_arch_opt_value) String(r24kef2_1) Value(51)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kef2_1) Value(53) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kef) Value(52) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kef2_1) Value(53)
|
||||
Enum(mips_arch_opt_value) String(r24kef) Value(52)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kef) Value(54) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kef1_1) Value(53) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kef) Value(54)
|
||||
Enum(mips_arch_opt_value) String(r24kef1_1) Value(53)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kef1_1) Value(55) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kefx) Value(54) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kef1_1) Value(55)
|
||||
Enum(mips_arch_opt_value) String(r24kefx) Value(54)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kefx) Value(56) Canonical
|
||||
Enum(mips_arch_opt_value) String(24kex) Value(55) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kefx) Value(56)
|
||||
Enum(mips_arch_opt_value) String(r24kex) Value(55)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kex) Value(57) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kc) Value(56) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kex) Value(57)
|
||||
Enum(mips_arch_opt_value) String(r34kc) Value(56)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kc) Value(58) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kf2_1) Value(57) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kc) Value(58)
|
||||
Enum(mips_arch_opt_value) String(r34kf2_1) Value(57)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kf2_1) Value(59) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kf) Value(58) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kf2_1) Value(59)
|
||||
Enum(mips_arch_opt_value) String(r34kf) Value(58)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kf) Value(60) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kf1_1) Value(59) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kf) Value(60)
|
||||
Enum(mips_arch_opt_value) String(r34kf1_1) Value(59)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kf1_1) Value(61) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kfx) Value(60) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kf1_1) Value(61)
|
||||
Enum(mips_arch_opt_value) String(r34kfx) Value(60)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kfx) Value(62) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kx) Value(61) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kfx) Value(62)
|
||||
Enum(mips_arch_opt_value) String(r34kx) Value(61)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kx) Value(63) Canonical
|
||||
Enum(mips_arch_opt_value) String(34kn) Value(62) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kx) Value(63)
|
||||
Enum(mips_arch_opt_value) String(r34kn) Value(62)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kn) Value(64) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kc) Value(63) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kn) Value(64)
|
||||
Enum(mips_arch_opt_value) String(r74kc) Value(63)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kc) Value(65) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kf2_1) Value(64) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kc) Value(65)
|
||||
Enum(mips_arch_opt_value) String(r74kf2_1) Value(64)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf2_1) Value(66) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kf) Value(65) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf2_1) Value(66)
|
||||
Enum(mips_arch_opt_value) String(r74kf) Value(65)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf) Value(67) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kf1_1) Value(66) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf) Value(67)
|
||||
Enum(mips_arch_opt_value) String(r74kf1_1) Value(66)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf1_1) Value(68) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kfx) Value(67) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf1_1) Value(68)
|
||||
Enum(mips_arch_opt_value) String(r74kfx) Value(67)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kfx) Value(69) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kx) Value(68) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kfx) Value(69)
|
||||
Enum(mips_arch_opt_value) String(r74kx) Value(68)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kx) Value(70) Canonical
|
||||
Enum(mips_arch_opt_value) String(74kf3_2) Value(69) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kx) Value(70)
|
||||
Enum(mips_arch_opt_value) String(r74kf3_2) Value(69)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf3_2) Value(71) Canonical
|
||||
Enum(mips_arch_opt_value) String(1004kc) Value(70) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf3_2) Value(71)
|
||||
Enum(mips_arch_opt_value) String(r1004kc) Value(70)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kc) Value(72) Canonical
|
||||
Enum(mips_arch_opt_value) String(1004kf2_1) Value(71) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kc) Value(72)
|
||||
Enum(mips_arch_opt_value) String(r1004kf2_1) Value(71)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kf2_1) Value(73) Canonical
|
||||
Enum(mips_arch_opt_value) String(1004kf) Value(72) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kf2_1) Value(73)
|
||||
Enum(mips_arch_opt_value) String(r1004kf) Value(72)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kf) Value(74) Canonical
|
||||
Enum(mips_arch_opt_value) String(1004kf1_1) Value(73) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kf) Value(74)
|
||||
Enum(mips_arch_opt_value) String(r1004kf1_1) Value(73)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kf1_1) Value(75) Canonical
|
||||
Enum(mips_arch_opt_value) String(5kc) Value(74) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kf1_1) Value(75)
|
||||
Enum(mips_arch_opt_value) String(r5kc) Value(74)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5kc) Value(76) Canonical
|
||||
Enum(mips_arch_opt_value) String(5kf) Value(75) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5kc) Value(76)
|
||||
Enum(mips_arch_opt_value) String(r5kf) Value(75)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5kf) Value(77) Canonical
|
||||
Enum(mips_arch_opt_value) String(20kc) Value(76) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5kf) Value(77)
|
||||
Enum(mips_arch_opt_value) String(r20kc) Value(76)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(20kc) Value(78) Canonical
|
||||
Enum(mips_arch_opt_value) String(sb1) Value(77) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r20kc) Value(78)
|
||||
Enum(mips_arch_opt_value) String(sb1a) Value(78) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sb1) Value(79) Canonical
|
||||
Enum(mips_arch_opt_value) String(sr71000) Value(79) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sb1a) Value(80) Canonical
|
||||
Enum(mips_arch_opt_value) String(sr71k) Value(79)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sr71000) Value(81) Canonical
|
||||
Enum(mips_arch_opt_value) String(xlr) Value(80) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sr71k) Value(81)
|
||||
Enum(mips_arch_opt_value) String(loongson3a) Value(81) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(xlr) Value(82) Canonical
|
||||
Enum(mips_arch_opt_value) String(octeon) Value(82) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(loongson3a) Value(83) Canonical
|
||||
Enum(mips_arch_opt_value) String(octeon+) Value(83) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(octeon) Value(84) Canonical
|
||||
Enum(mips_arch_opt_value) String(octeon2) Value(84) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(octeon+) Value(85) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(octeon2) Value(86) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(xlp) Value(87) Canonical
|
||||
Enum(mips_arch_opt_value) String(xlp) Value(85) Canonical
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -174,9 +174,6 @@ struct mips_cpu_info {
|
|||
#define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
|
||||
#endif
|
||||
|
||||
/* The ISA compression flags that are currently in effect. */
|
||||
#define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
|
||||
|
||||
/* Generate mips16 code */
|
||||
#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
|
||||
/* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
|
||||
|
|
@ -377,7 +374,7 @@ struct mips_cpu_info {
|
|||
else \
|
||||
builtin_define ("__mips_fpr=32"); \
|
||||
\
|
||||
if (mips_base_compression_flags & MASK_MIPS16) \
|
||||
if (mips_base_mips16) \
|
||||
builtin_define ("__mips16"); \
|
||||
\
|
||||
if (TARGET_MIPS3D) \
|
||||
|
|
@ -386,9 +383,6 @@ struct mips_cpu_info {
|
|||
if (TARGET_SMARTMIPS) \
|
||||
builtin_define ("__mips_smartmips"); \
|
||||
\
|
||||
if (mips_base_compression_flags & MASK_MICROMIPS) \
|
||||
builtin_define ("__mips_micromips"); \
|
||||
\
|
||||
if (TARGET_MCU) \
|
||||
builtin_define ("__mips_mcu"); \
|
||||
\
|
||||
|
|
@ -708,7 +702,7 @@ struct mips_cpu_info {
|
|||
|march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
|
||||
%{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
|
||||
%{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
|
||||
|march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
|
||||
|march=34k*|march=74k*|march=1004k*: -mips32r2} \
|
||||
%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
|
||||
|march=xlr|march=loongson3a: -mips64} \
|
||||
%{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
|
||||
|
|
@ -722,7 +716,7 @@ struct mips_cpu_info {
|
|||
"%{mhard-float|msoft-float|mno-float|march=mips*:; \
|
||||
march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
|
||||
|march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
|
||||
|march=m14k*|march=octeon|march=xlr: -msoft-float; \
|
||||
|march=octeon|march=xlr: -msoft-float; \
|
||||
march=*: -mhard-float}"
|
||||
|
||||
/* A spec condition that matches 32-bit options. It only works if
|
||||
|
|
@ -995,8 +989,7 @@ struct mips_cpu_info {
|
|||
|| ISA_MIPS64R2))
|
||||
|
||||
/* ISA has lwxs instruction (load w/scaled index address. */
|
||||
#define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
|
||||
&& !TARGET_MIPS16)
|
||||
#define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
|
||||
|
||||
/* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
|
||||
#define ISA_HAS_LBX (TARGET_OCTEON2)
|
||||
|
|
@ -1019,8 +1012,7 @@ struct mips_cpu_info {
|
|||
and "addiu $4,$4,1". */
|
||||
#define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
|
||||
&& !TARGET_MIPS3900 \
|
||||
&& !TARGET_MIPS16 \
|
||||
&& !TARGET_MICROMIPS)
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* Likewise mtc1 and mfc1. */
|
||||
#define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
|
||||
|
|
@ -1131,7 +1123,6 @@ struct mips_cpu_info {
|
|||
%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
|
||||
%{mips32*} %{mips64*} \
|
||||
%{mips16} %{mno-mips16:-no-mips16} \
|
||||
%{mmicromips} %{mno-micromips} \
|
||||
%{mips3d} %{mno-mips3d:-no-mips3d} \
|
||||
%{mdmx} %{mno-mdmx:-no-mdmx} \
|
||||
%{mdsp} %{mno-dsp} \
|
||||
|
|
@ -1681,8 +1672,6 @@ struct mips_cpu_info {
|
|||
((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
|
||||
#define M16_REG_P(REGNO) \
|
||||
(((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
|
||||
#define M16STORE_REG_P(REGNO) \
|
||||
(((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
|
||||
#define FP_REG_P(REGNO) \
|
||||
((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
|
||||
#define MD_REG_P(REGNO) \
|
||||
|
|
@ -2045,7 +2034,6 @@ enum reg_class
|
|||
#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
|
||||
#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
|
||||
#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
|
||||
#define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
|
||||
|
||||
/* The HI and LO registers can only be reloaded via the general
|
||||
registers. Condition code registers can only be loaded to the
|
||||
|
|
@ -2464,32 +2452,17 @@ typedef struct mips_args {
|
|||
all calls should use assembly macros. Otherwise, all indirect
|
||||
calls should use "jr" or "jalr"; we will arrange to restore $gp
|
||||
afterwards if necessary. Finally, we can only generate direct
|
||||
calls for -mabicalls by temporarily switching to non-PIC mode.
|
||||
|
||||
For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
|
||||
instruction is in the delay slot of jal(r). */
|
||||
calls for -mabicalls by temporarily switching to non-PIC mode. */
|
||||
#define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
|
||||
(TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
|
||||
? "%*" INSN "\t%" #TARGET_OPNO "%/" \
|
||||
: (REG_P (OPERANDS[TARGET_OPNO]) \
|
||||
&& mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
|
||||
? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
|
||||
"1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
|
||||
: REG_P (OPERANDS[TARGET_OPNO]) \
|
||||
? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
|
||||
? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
|
||||
"1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
|
||||
: TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
|
||||
? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
|
||||
: "%*" INSN "r\t%" #TARGET_OPNO "%/") \
|
||||
? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
|
||||
: MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
|
||||
|
||||
/* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
|
||||
"jrc" when nop is in the delay slot of "jr". */
|
||||
|
||||
#define MICROMIPS_J(INSN, OPERANDS, OPNO) \
|
||||
(TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
|
||||
? "%*j\t%" #OPNO "%/" \
|
||||
: REG_P (OPERANDS[OPNO]) \
|
||||
? "%*jr%:\t%" #OPNO \
|
||||
: MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
|
||||
|
||||
|
||||
/* Control the assembler format that we output. */
|
||||
|
||||
|
|
@ -2904,7 +2877,7 @@ extern enum processor mips_tune; /* which cpu to schedule for */
|
|||
extern int mips_isa; /* architectural level */
|
||||
extern const struct mips_cpu_info *mips_arch_info;
|
||||
extern const struct mips_cpu_info *mips_tune_info;
|
||||
extern unsigned int mips_base_compression_flags;
|
||||
extern bool mips_base_mips16;
|
||||
extern GTY(()) struct target_globals *mips16_globals;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -342,14 +342,13 @@
|
|||
;; syncloop memory atomic operation implemented as a sync loop
|
||||
;; nop no operation
|
||||
;; ghost an instruction that produces no real code
|
||||
;; multimem microMIPS multiword load and store
|
||||
(define_attr "type"
|
||||
"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
|
||||
prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
|
||||
shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
|
||||
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
|
||||
frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
|
||||
multi,atomic,syncloop,nop,ghost,multimem"
|
||||
multi,atomic,syncloop,nop,ghost"
|
||||
(cond [(eq_attr "jal" "!unset") (const_string "call")
|
||||
(eq_attr "got" "load") (const_string "load")
|
||||
|
||||
|
|
@ -414,15 +413,9 @@
|
|||
|
||||
;; Length of instruction in bytes.
|
||||
(define_attr "length" ""
|
||||
(cond [(and (eq_attr "extended_mips16" "yes")
|
||||
(match_test "TARGET_MIPS16"))
|
||||
(const_int 8)
|
||||
|
||||
;; Direct microMIPS branch instructions have a range of
|
||||
;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
|
||||
;; If a branch is outside this range, we have a choice of two
|
||||
;; sequences.
|
||||
;;
|
||||
(cond [;; Direct branch instructions have a range of [-0x20000,0x1fffc],
|
||||
;; relative to the address of the delay slot. If a branch is
|
||||
;; outside this range, we have a choice of two sequences.
|
||||
;; For PIC, an out-of-range branch like:
|
||||
;;
|
||||
;; bne r1,r2,target
|
||||
|
|
@ -458,15 +451,8 @@
|
|||
;; from the shorten_branches reference address.
|
||||
(and (eq_attr "type" "branch")
|
||||
(not (match_test "TARGET_MIPS16")))
|
||||
(cond [;; Any variant can handle the 17-bit range.
|
||||
(and (le (minus (match_dup 0) (pc)) (const_int 65532))
|
||||
(le (minus (pc) (match_dup 0)) (const_int 65534)))
|
||||
(const_int 4)
|
||||
|
||||
;; The 18-bit range is OK other than for microMIPS.
|
||||
(and (not (match_test "TARGET_MICROMIPS"))
|
||||
(and (le (minus (match_dup 0) (pc)) (const_int 131064))
|
||||
(le (minus (pc) (match_dup 0)) (const_int 131068))))
|
||||
(cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
|
||||
(le (minus (pc) (match_dup 0)) (const_int 131068)))
|
||||
(const_int 4)
|
||||
|
||||
;; The non-PIC case: branch, first delay slot, and J.
|
||||
|
|
@ -726,9 +712,6 @@
|
|||
;; modes.
|
||||
(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
|
||||
|
||||
(define_mode_iterator MOVEP1 [SI SF])
|
||||
(define_mode_iterator MOVEP2 [SI SF])
|
||||
|
||||
;; This mode iterator allows :HILO to be used as the mode of the
|
||||
;; concatenated HI and LO registers.
|
||||
(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
|
||||
|
|
@ -3954,7 +3937,7 @@
|
|||
(define_insn "mov_<load>l"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=d")
|
||||
(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
|
||||
(match_operand:QI 2 "memory_operand" "ZC")]
|
||||
(match_operand:QI 2 "memory_operand" "m")]
|
||||
UNSPEC_LOAD_LEFT))]
|
||||
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
|
||||
"<load>l\t%0,%2"
|
||||
|
|
@ -3964,7 +3947,7 @@
|
|||
(define_insn "mov_<load>r"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=d")
|
||||
(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
|
||||
(match_operand:QI 2 "memory_operand" "ZC")
|
||||
(match_operand:QI 2 "memory_operand" "m")
|
||||
(match_operand:GPR 3 "register_operand" "0")]
|
||||
UNSPEC_LOAD_RIGHT))]
|
||||
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
|
||||
|
|
@ -3975,7 +3958,7 @@
|
|||
(define_insn "mov_<store>l"
|
||||
[(set (match_operand:BLK 0 "memory_operand" "=m")
|
||||
(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
|
||||
(match_operand:QI 2 "memory_operand" "ZC")]
|
||||
(match_operand:QI 2 "memory_operand" "m")]
|
||||
UNSPEC_STORE_LEFT))]
|
||||
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
|
||||
"<store>l\t%z1,%2"
|
||||
|
|
@ -3985,7 +3968,7 @@
|
|||
(define_insn "mov_<store>r"
|
||||
[(set (match_operand:BLK 0 "memory_operand" "+m")
|
||||
(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
|
||||
(match_operand:QI 2 "memory_operand" "ZC")
|
||||
(match_operand:QI 2 "memory_operand" "m")
|
||||
(match_dup 0)]
|
||||
UNSPEC_STORE_RIGHT))]
|
||||
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
|
||||
|
|
@ -5464,14 +5447,6 @@
|
|||
(pc)))]
|
||||
"!TARGET_MIPS16"
|
||||
{
|
||||
/* For a simple BNEZ or BEQZ microMIPS branch. */
|
||||
if (TARGET_MICROMIPS
|
||||
&& operands[3] == const0_rtx
|
||||
&& get_attr_length (insn) <= 8)
|
||||
return mips_output_conditional_branch (insn, operands,
|
||||
"%*b%C1z%:\t%2,%0",
|
||||
"%*b%N1z%:\t%2,%0");
|
||||
|
||||
return mips_output_conditional_branch (insn, operands,
|
||||
MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
|
||||
MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
|
||||
|
|
@ -5488,14 +5463,6 @@
|
|||
(label_ref (match_operand 0 "" ""))))]
|
||||
"!TARGET_MIPS16"
|
||||
{
|
||||
/* For a simple BNEZ or BEQZ microMIPS branch. */
|
||||
if (TARGET_MICROMIPS
|
||||
&& operands[3] == const0_rtx
|
||||
&& get_attr_length (insn) <= 8)
|
||||
return mips_output_conditional_branch (insn, operands,
|
||||
"%*b%N0z%:\t%2,%1",
|
||||
"%*b%C0z%:\t%2,%1");
|
||||
|
||||
return mips_output_conditional_branch (insn, operands,
|
||||
MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
|
||||
MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
|
||||
|
|
@ -5799,14 +5766,7 @@
|
|||
[(set (pc)
|
||||
(label_ref (match_operand 0)))]
|
||||
"!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
|
||||
{
|
||||
/* Use a branch for microMIPS. The assembler will choose
|
||||
a 16-bit branch, a 32-bit branch, or a 32-bit jump. */
|
||||
if (TARGET_MICROMIPS && !TARGET_ABICALLS_PIC2)
|
||||
return "%*b\t%l0%/";
|
||||
else
|
||||
return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/");
|
||||
}
|
||||
{ return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); }
|
||||
[(set_attr "type" "jump")])
|
||||
|
||||
(define_insn "*jump_pic"
|
||||
|
|
@ -5869,12 +5829,7 @@
|
|||
(define_insn "indirect_jump_<mode>"
|
||||
[(set (pc) (match_operand:P 0 "register_operand" "d"))]
|
||||
""
|
||||
{
|
||||
if (TARGET_MICROMIPS)
|
||||
return "%*jr%:\t%0";
|
||||
else
|
||||
return "%*j\t%0%/";
|
||||
}
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
|
|
@ -5918,12 +5873,7 @@
|
|||
(match_operand:P 0 "register_operand" "d"))
|
||||
(use (label_ref (match_operand 1 "" "")))]
|
||||
""
|
||||
{
|
||||
if (TARGET_MICROMIPS)
|
||||
return "%*jr%:\t%0";
|
||||
else
|
||||
return "%*j\t%0%/";
|
||||
}
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
|
|
@ -6144,12 +6094,7 @@
|
|||
[(any_return)
|
||||
(use (match_operand 0 "pmode_register_operand" ""))]
|
||||
""
|
||||
{
|
||||
if (TARGET_MICROMIPS)
|
||||
return "%*jr%:\t%0";
|
||||
else
|
||||
return "%*j\t%0%/";
|
||||
}
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
|
|
@ -6405,12 +6350,7 @@
|
|||
[(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
|
||||
(match_operand 1 "" ""))]
|
||||
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
|
||||
{
|
||||
if (TARGET_MICROMIPS)
|
||||
return MICROMIPS_J ("j", operands, 0);
|
||||
else
|
||||
return MIPS_CALL ("j", operands, 0, 1);
|
||||
}
|
||||
{ return MIPS_CALL ("j", operands, 0, 1); }
|
||||
[(set_attr "jal" "indirect,direct")
|
||||
(set_attr "jal_macro" "no")])
|
||||
|
||||
|
|
@ -6431,12 +6371,7 @@
|
|||
(call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
|
||||
(match_operand 2 "" "")))]
|
||||
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
|
||||
{
|
||||
if (TARGET_MICROMIPS)
|
||||
return MICROMIPS_J ("j", operands, 1);
|
||||
else
|
||||
return MIPS_CALL ("j", operands, 1, 2);
|
||||
}
|
||||
{ return MIPS_CALL ("j", operands, 1, 2); }
|
||||
[(set_attr "jal" "indirect,direct")
|
||||
(set_attr "jal_macro" "no")])
|
||||
|
||||
|
|
@ -6448,12 +6383,7 @@
|
|||
(call (mem:SI (match_dup 1))
|
||||
(match_dup 2)))]
|
||||
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
|
||||
{
|
||||
if (TARGET_MICROMIPS)
|
||||
return MICROMIPS_J ("j", operands, 1);
|
||||
else
|
||||
return MIPS_CALL ("j", operands, 1, 2);
|
||||
}
|
||||
{ return MIPS_CALL ("j", operands, 1, 2); }
|
||||
[(set_attr "jal" "indirect,direct")
|
||||
(set_attr "jal_macro" "no")])
|
||||
|
||||
|
|
@ -6699,7 +6629,7 @@
|
|||
|
||||
|
||||
(define_insn "prefetch"
|
||||
[(prefetch (match_operand:QI 0 "address_operand" "ZD")
|
||||
[(prefetch (match_operand:QI 0 "address_operand" "p")
|
||||
(match_operand 1 "const_int_operand" "n")
|
||||
(match_operand 2 "const_int_operand" "n"))]
|
||||
"ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
|
||||
|
|
@ -6992,9 +6922,6 @@
|
|||
; MIPS fixed-point instructions.
|
||||
(include "mips-fixed.md")
|
||||
|
||||
; microMIPS patterns.
|
||||
(include "micromips.md")
|
||||
|
||||
; ST-Microelectronics Loongson-2E/2F-specific patterns.
|
||||
(include "loongson.md")
|
||||
|
||||
|
|
|
|||
|
|
@ -217,13 +217,9 @@ mhard-float
|
|||
Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
|
||||
Allow the use of hardware floating-point ABI and instructions
|
||||
|
||||
minterlink-compressed
|
||||
Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
|
||||
Generate code that is link-compatible with MIPS16 and microMIPS code.
|
||||
|
||||
minterlink-mips16
|
||||
Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
|
||||
An alias for minterlink-compressed provided for backward-compatibility.
|
||||
Target Report Var(TARGET_INTERLINK_MIPS16) Init(0)
|
||||
Generate code that can be safely linked with MIPS16 code.
|
||||
|
||||
mips
|
||||
Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
|
||||
|
|
@ -265,10 +261,6 @@ mmemcpy
|
|||
Target Report Mask(MEMCPY)
|
||||
Don't optimize block moves
|
||||
|
||||
mmicromips
|
||||
Target Report Mask(MICROMIPS)
|
||||
Use microMIPS instructions
|
||||
|
||||
mmt
|
||||
Target Report Var(TARGET_MT)
|
||||
Allow the use of MT instructions
|
||||
|
|
|
|||
|
|
@ -122,15 +122,6 @@
|
|||
? M16_REG_P (REGNO (op))
|
||||
: GP_REG_P (REGNO (op))")))
|
||||
|
||||
(define_predicate "movep_src_register"
|
||||
(and (match_code "reg")
|
||||
(ior (match_test ("IN_RANGE (REGNO (op), 2, 3)"))
|
||||
(match_test ("IN_RANGE (REGNO (op), 16, 20)")))))
|
||||
|
||||
(define_predicate "movep_src_operand"
|
||||
(ior (match_operand 0 "const_0_operand")
|
||||
(match_operand 0 "movep_src_register")))
|
||||
|
||||
(define_predicate "lo_operand"
|
||||
(and (match_code "reg")
|
||||
(match_test "REGNO (op) == LO_REGNUM")))
|
||||
|
|
@ -380,8 +371,3 @@
|
|||
(define_predicate "mem_noofs_operand"
|
||||
(and (match_code "mem")
|
||||
(match_code "reg" "0")))
|
||||
|
||||
;; Return 1 if the operand is in non-volatile memory.
|
||||
(define_predicate "non_volatile_mem_operand"
|
||||
(and (match_operand 0 "memory_operand")
|
||||
(not (match_test "MEM_VOLATILE_P (op)"))))
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@
|
|||
;; Can be removed in favor of atomic_compare_and_swap below.
|
||||
(define_insn "sync_compare_and_swap<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
|
||||
(match_operand:GPR 3 "arith_operand" "I,d")]
|
||||
|
|
@ -89,7 +89,7 @@
|
|||
;; Helper insn for mips_expand_atomic_qihi.
|
||||
(define_insn "compare_and_swap_12"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d,&d")
|
||||
(match_operand:SI 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:SI 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
|
||||
(match_operand:SI 3 "register_operand" "d,d")
|
||||
|
|
@ -106,7 +106,7 @@
|
|||
(set_attr "sync_insn1_op2" "5")])
|
||||
|
||||
(define_insn "sync_add<mode>"
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+ZR,ZR")
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+R,R")
|
||||
(unspec_volatile:GPR
|
||||
[(plus:GPR (match_dup 0)
|
||||
(match_operand:GPR 1 "arith_operand" "I,d"))]
|
||||
|
|
@ -134,7 +134,7 @@
|
|||
|
||||
;; Helper insn for sync_<optab><mode>
|
||||
(define_insn "sync_<optab>_12"
|
||||
[(set (match_operand:SI 0 "memory_operand" "+ZR")
|
||||
[(set (match_operand:SI 0 "memory_operand" "+R")
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "register_operand" "d")
|
||||
|
|
@ -174,7 +174,7 @@
|
|||
;; Helper insn for sync_old_<optab><mode>
|
||||
(define_insn "sync_old_<optab>_12"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(match_operand:SI 1 "memory_operand" "+ZR"))
|
||||
(match_operand:SI 1 "memory_operand" "+R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 2 "register_operand" "d")
|
||||
|
|
@ -217,7 +217,7 @@
|
|||
(define_insn "sync_new_<optab>_12"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 1 "memory_operand" "+ZR")
|
||||
[(match_operand:SI 1 "memory_operand" "+R")
|
||||
(match_operand:SI 2 "register_operand" "d")
|
||||
(match_operand:SI 3 "register_operand" "d")
|
||||
(atomic_hiqi_op:SI (match_dup 0)
|
||||
|
|
@ -257,7 +257,7 @@
|
|||
|
||||
;; Helper insn for sync_nand<mode>
|
||||
(define_insn "sync_nand_12"
|
||||
[(set (match_operand:SI 0 "memory_operand" "+ZR")
|
||||
[(set (match_operand:SI 0 "memory_operand" "+R")
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "register_operand" "d")
|
||||
|
|
@ -296,7 +296,7 @@
|
|||
;; Helper insn for sync_old_nand<mode>
|
||||
(define_insn "sync_old_nand_12"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(match_operand:SI 1 "memory_operand" "+ZR"))
|
||||
(match_operand:SI 1 "memory_operand" "+R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 2 "register_operand" "d")
|
||||
|
|
@ -337,7 +337,7 @@
|
|||
(define_insn "sync_new_nand_12"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 1 "memory_operand" "+ZR")
|
||||
[(match_operand:SI 1 "memory_operand" "+R")
|
||||
(match_operand:SI 2 "register_operand" "d")
|
||||
(match_operand:SI 3 "register_operand" "d")
|
||||
(match_operand:SI 4 "reg_or_0_operand" "dJ")]
|
||||
|
|
@ -360,7 +360,7 @@
|
|||
(set_attr "sync_insn1_op2" "4")])
|
||||
|
||||
(define_insn "sync_sub<mode>"
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+ZR")
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+R")
|
||||
(unspec_volatile:GPR
|
||||
[(minus:GPR (match_dup 0)
|
||||
(match_operand:GPR 1 "register_operand" "d"))]
|
||||
|
|
@ -374,7 +374,7 @@
|
|||
;; Can be removed in favor of atomic_fetch_add below.
|
||||
(define_insn "sync_old_add<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
[(plus:GPR (match_dup 1)
|
||||
|
|
@ -389,7 +389,7 @@
|
|||
|
||||
(define_insn "sync_old_sub<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
[(minus:GPR (match_dup 1)
|
||||
|
|
@ -404,7 +404,7 @@
|
|||
|
||||
(define_insn "sync_new_add<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(plus:GPR (match_operand:GPR 1 "memory_operand" "+ZR,ZR")
|
||||
(plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
|
||||
(match_operand:GPR 2 "arith_operand" "I,d")))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
|
|
@ -420,7 +420,7 @@
|
|||
|
||||
(define_insn "sync_new_sub<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d")
|
||||
(minus:GPR (match_operand:GPR 1 "memory_operand" "+ZR")
|
||||
(minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
|
||||
(match_operand:GPR 2 "register_operand" "d")))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
|
|
@ -435,7 +435,7 @@
|
|||
(set_attr "sync_insn1_op2" "2")])
|
||||
|
||||
(define_insn "sync_<optab><mode>"
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+ZR,ZR")
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+R,R")
|
||||
(unspec_volatile:GPR
|
||||
[(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
|
||||
(match_dup 0))]
|
||||
|
|
@ -448,7 +448,7 @@
|
|||
|
||||
(define_insn "sync_old_<optab><mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
[(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
|
||||
|
|
@ -463,7 +463,7 @@
|
|||
|
||||
(define_insn "sync_new_<optab><mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
[(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
|
||||
|
|
@ -478,7 +478,7 @@
|
|||
(set_attr "sync_insn1_op2" "2")])
|
||||
|
||||
(define_insn "sync_nand<mode>"
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+ZR,ZR")
|
||||
[(set (match_operand:GPR 0 "memory_operand" "+R,R")
|
||||
(unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
|
|
@ -490,7 +490,7 @@
|
|||
|
||||
(define_insn "sync_old_nand<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
|
|
@ -504,7 +504,7 @@
|
|||
|
||||
(define_insn "sync_new_nand<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
|
||||
UNSPEC_SYNC_NEW_OP))]
|
||||
|
|
@ -519,7 +519,7 @@
|
|||
|
||||
(define_insn "sync_lock_test_and_set<mode>"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(match_operand:GPR 1 "memory_operand" "+ZR,ZR"))
|
||||
(match_operand:GPR 1 "memory_operand" "+R,R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
|
||||
UNSPEC_SYNC_EXCHANGE))]
|
||||
|
|
@ -546,7 +546,7 @@
|
|||
|
||||
(define_insn "test_and_set_12"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(match_operand:SI 1 "memory_operand" "+ZR"))
|
||||
(match_operand:SI 1 "memory_operand" "+R"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
|
||||
(match_operand:SI 3 "register_operand" "d")
|
||||
|
|
@ -576,7 +576,7 @@
|
|||
;; TODO: the obscuring unspec can be relaxed for permissive memory
|
||||
;; models.
|
||||
;; Same applies to other atomic_* patterns.
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "memory_operand" "+ZR,ZR")
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "memory_operand" "+R,R")
|
||||
(match_operand:GPR 3 "reg_or_0_operand" "dJ,dJ")]
|
||||
UNSPEC_ATOMIC_COMPARE_AND_SWAP))
|
||||
(set (match_operand:GPR 1 "register_operand" "=&d,&d")
|
||||
|
|
@ -629,7 +629,7 @@
|
|||
|
||||
(define_insn "atomic_exchange<mode>_llsc"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZR,ZR")]
|
||||
(unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+R,R")]
|
||||
UNSPEC_ATOMIC_EXCHANGE))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
|
||||
|
|
@ -684,7 +684,7 @@
|
|||
|
||||
(define_insn "atomic_fetch_add<mode>_llsc"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
|
||||
(unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZR,ZR")]
|
||||
(unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+R,R")]
|
||||
UNSPEC_ATOMIC_FETCH_OP))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:GPR
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@
|
|||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
MULTILIB_OPTIONS = EL/EB mips32/mips32r2/mips64/mips64r2 mips16/mmicromips msoft-float/mfp64 mcode-readable=no
|
||||
MULTILIB_DIRNAMES = el eb mips32 mips32r2 mips64 mips64r2 mips16 micromips sof f64 spram
|
||||
MULTILIB_OPTIONS = EL/EB mips32/mips32r2/mips64/mips64r2 mips16 msoft-float/mfp64 mcode-readable=no
|
||||
MULTILIB_DIRNAMES = el eb mips32 mips32r2 mips64 mips64r2 mips16 sof f64 spram
|
||||
MULTILIB_MATCHES = EL=mel EB=meb
|
||||
|
||||
# The -mfp64 option is only valid in conjunction with -mips32r2.
|
||||
|
|
|
|||
|
|
@ -25706,37 +25706,6 @@ if test $gcc_cv_as_mips_gnu_attribute = yes; then
|
|||
|
||||
$as_echo "#define HAVE_AS_GNU_ATTRIBUTE 1" >>confdefs.h
|
||||
|
||||
fi
|
||||
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .micromips support" >&5
|
||||
$as_echo_n "checking assembler for .micromips support... " >&6; }
|
||||
if test "${gcc_cv_as_micromips_support+set}" = set; then :
|
||||
$as_echo_n "(cached) " >&6
|
||||
else
|
||||
gcc_cv_as_micromips_support=no
|
||||
if test x$gcc_cv_as != x; then
|
||||
$as_echo '.set micromips' > conftest.s
|
||||
if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'
|
||||
{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
|
||||
(eval $ac_try) 2>&5
|
||||
ac_status=$?
|
||||
$as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
|
||||
test $ac_status = 0; }; }
|
||||
then
|
||||
gcc_cv_as_micromips_support=yes
|
||||
else
|
||||
echo "configure: failed program was" >&5
|
||||
cat conftest.s >&5
|
||||
fi
|
||||
rm -f conftest.o conftest.s
|
||||
fi
|
||||
fi
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_micromips_support" >&5
|
||||
$as_echo "$gcc_cv_as_micromips_support" >&6; }
|
||||
if test $gcc_cv_as_micromips_support = yes; then
|
||||
|
||||
$as_echo "#define HAVE_GAS_MICROMIPS 1" >>confdefs.h
|
||||
|
||||
fi
|
||||
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .dtprelword support" >&5
|
||||
|
|
|
|||
|
|
@ -4036,12 +4036,6 @@ LCF0:
|
|||
[AC_DEFINE(HAVE_AS_GNU_ATTRIBUTE, 1,
|
||||
[Define if your assembler supports .gnu_attribute.])])
|
||||
|
||||
gcc_GAS_CHECK_FEATURE([.micromips support],
|
||||
gcc_cv_as_micromips_support,,,
|
||||
[.set micromips],,
|
||||
[AC_DEFINE(HAVE_GAS_MICROMIPS, 1,
|
||||
[Define if your assembler supports the .set micromips directive])])
|
||||
|
||||
gcc_GAS_CHECK_FEATURE([.dtprelword support],
|
||||
gcc_cv_as_mips_dtprelword, [2,18,0],,
|
||||
[.section .tdata,"awT",@progbits
|
||||
|
|
|
|||
|
|
@ -3053,25 +3053,6 @@ not that within individual functions. Mixed MIPS16 and non-MIPS16 code
|
|||
may interact badly with some GCC extensions such as @code{__builtin_apply}
|
||||
(@pxref{Constructing Calls}).
|
||||
|
||||
@item micromips/nomicromips
|
||||
@cindex @code{micromips} attribute
|
||||
@cindex @code{nomicromips} attribute
|
||||
|
||||
On MIPS targets, you can use the @code{micromips} and @code{nomicromips}
|
||||
function attributes to locally select or turn off microMIPS code generation.
|
||||
A function with the @code{micromips} attribute is emitted as microMIPS code,
|
||||
while microMIPS code generation is disabled for functions with the
|
||||
@code{nomicromips} attribute. These attributes override the
|
||||
@option{-mmicromips} and @option{-mno-micromips} options on the command line
|
||||
(@pxref{MIPS Options}).
|
||||
|
||||
When compiling files containing mixed microMIPS and non-microMIPS code, the
|
||||
preprocessor symbol @code{__mips_micromips} reflects the setting on the
|
||||
command line,
|
||||
not that within individual functions. Mixed microMIPS and non-microMIPS code
|
||||
may interact badly with some GCC extensions such as @code{__builtin_apply}
|
||||
(@pxref{Constructing Calls}).
|
||||
|
||||
@item model (@var{model-name})
|
||||
@cindex function addressability on the M32R/D
|
||||
@cindex variable addressability on the IA-64
|
||||
|
|
@ -3174,13 +3155,6 @@ is an NMI handler. The compiler generates function entry and
|
|||
exit sequences suitable for use in an NMI handler when this
|
||||
attribute is present.
|
||||
|
||||
@item nocompression
|
||||
@cindex @code{nocompression} attribute
|
||||
On MIPS targets, you can use the @code{nocompression} function attribute
|
||||
to locally turn off MIPS16 and microMIPS code generation. This attribute
|
||||
overrides the @option{-mips16} and @option{-mmicromips} options on the
|
||||
command line (@pxref{MIPS Options}).
|
||||
|
||||
@item no_instrument_function
|
||||
@cindex @code{no_instrument_function} function attribute
|
||||
@opindex finstrument-functions
|
||||
|
|
|
|||
|
|
@ -740,7 +740,6 @@ Objective-C and Objective-C++ Dialects}.
|
|||
-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol
|
||||
-mips64 -mips64r2 @gol
|
||||
-mips16 -mno-mips16 -mflip-mips16 @gol
|
||||
-minterlink-compressed -mno-interlink-compressed @gol
|
||||
-minterlink-mips16 -mno-interlink-mips16 @gol
|
||||
-mabi=@var{abi} -mabicalls -mno-abicalls @gol
|
||||
-mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol
|
||||
|
|
@ -748,7 +747,6 @@ Objective-C and Objective-C++ Dialects}.
|
|||
-mno-float -msingle-float -mdouble-float @gol
|
||||
-mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol
|
||||
-mmcu -mmno-mcu @gol
|
||||
-mmicromips -mno-micromips @gol
|
||||
-mfpu=@var{fpu-type} @gol
|
||||
-msmartmips -mno-smartmips @gol
|
||||
-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol
|
||||
|
|
@ -15882,7 +15880,6 @@ The processor names are:
|
|||
@samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
|
||||
@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
|
||||
@samp{m4k},
|
||||
@samp{m14k}, @samp{m14ke}, @samp{m14kec},
|
||||
@samp{octeon}, @samp{octeon+}, @samp{octeon2},
|
||||
@samp{orion},
|
||||
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
|
||||
|
|
@ -15996,25 +15993,17 @@ Generate MIPS16 code on alternating functions. This option is provided
|
|||
for regression testing of mixed MIPS16/non-MIPS16 code generation, and is
|
||||
not intended for ordinary use in compiling user code.
|
||||
|
||||
@item -minterlink-compressed
|
||||
@item -mno-interlink-compressed
|
||||
@opindex minterlink-compressed
|
||||
@opindex mno-interlink-compressed
|
||||
Require (do not require) that code using the standard (uncompressed) MIPS ISA
|
||||
be link-compatible with MIPS16 and microMIPS code, and vice versa.
|
||||
|
||||
For example, code using the standard ISA encoding cannot jump directly
|
||||
to MIPS16 or microMIPS code; it must either use a call or an indirect jump.
|
||||
@option{-minterlink-compressed} therefore disables direct jumps unless GCC
|
||||
knows that the target of the jump is not compressed.
|
||||
|
||||
@item -minterlink-mips16
|
||||
@itemx -mno-interlink-mips16
|
||||
@opindex minterlink-mips16
|
||||
@opindex mno-interlink-mips16
|
||||
Aliases of @option{-minterlink-compressed} and
|
||||
@option{-mno-interlink-compressed}. These options predate the microMIPS ASE
|
||||
and are retained for backwards compatiblity.
|
||||
Require (do not require) that non-MIPS16 code be link-compatible with
|
||||
MIPS16 code.
|
||||
|
||||
For example, non-MIPS16 code cannot jump directly to MIPS16 code;
|
||||
it must either use a call or an indirect jump. @option{-minterlink-mips16}
|
||||
therefore disables direct jumps unless GCC knows that the target of the
|
||||
jump is not MIPS16.
|
||||
|
||||
@item -mabi=32
|
||||
@itemx -mabi=o64
|
||||
|
|
@ -16229,16 +16218,6 @@ hardware floating-point support to be enabled.
|
|||
Use (do not use) the MIPS-3D ASE@. @xref{MIPS-3D Built-in Functions}.
|
||||
The option @option{-mips3d} implies @option{-mpaired-single}.
|
||||
|
||||
@item -mmicromips
|
||||
@itemx -mno-micromips
|
||||
@opindex mmicromips
|
||||
@opindex mno-mmicromips
|
||||
Generate (do not generate) microMIPS code.
|
||||
|
||||
MicroMIPS code generation can also be controlled on a per-function basis
|
||||
by means of @code{micromips} and @code{nomicromips} attributes.
|
||||
@xref{Function Attributes}, for more information.
|
||||
|
||||
@item -mmt
|
||||
@itemx -mno-mt
|
||||
@opindex mmt
|
||||
|
|
|
|||
|
|
@ -2916,19 +2916,6 @@ Floating-point zero.
|
|||
|
||||
@item R
|
||||
An address that can be used in a non-macro load or store.
|
||||
|
||||
@item ZC
|
||||
When compiling microMIPS code, this constraint matches a memory operand
|
||||
whose address is formed from a base register and a 12-bit offset. These
|
||||
operands can be used for microMIPS instructions such as @code{ll} and
|
||||
@code{sc}. When not compiling for microMIPS code, @code{ZC} is
|
||||
equivalent to @code{R}.
|
||||
|
||||
@item ZD
|
||||
When compiling microMIPS code, this constraint matches an address operand
|
||||
that is formed from a base register and a 12-bit offset. These operands
|
||||
can be used for microMIPS instructions such as @code{prefetch}. When
|
||||
not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}.
|
||||
@end table
|
||||
|
||||
@item Motorola 680x0---@file{config/m68k/constraints.md}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,34 @@
|
|||
2013-02-25 Catherine Moore <clm@codesourcery.com>
|
||||
|
||||
Revert:
|
||||
2013-02-24 Catherine Moore <clm@codesourcery.com>
|
||||
Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* gcc.target/mips/mips.exp: Add microMIPS support.
|
||||
* gcc.target/mips/umips-movep-2.c: New test.
|
||||
* gcc.target/mips/umips-lwp-2.c: New test.
|
||||
* gcc.target/mips/umips-swp-5.c: New test.
|
||||
* gcc.target/mips/umips-constraints-1.c: New test.
|
||||
* gcc.target/mips/umips-lwp-3.c: New test.
|
||||
* gcc.target/mips/umips-swp-6.c: New test.
|
||||
* gcc.target/mips/umips-constraints-2.c: New test.
|
||||
* gcc.target/mips/umips-save-restore-1.c: New test.
|
||||
* gcc.target/mips/umips-lwp-4.c: New test.
|
||||
* gcc.target/mips/umips-swp-7.c: New test.
|
||||
* gcc.target/mips/umips-save-restore-2.c: New test.
|
||||
* gcc.target/mips/umips-lwp-swp-volatile.c: New test.
|
||||
* gcc.target/mips/umips-lwp-5.c: New test.
|
||||
* gcc.target/mips/umips-save-restore-3.c: New test.
|
||||
* gcc.target/mips/umips-lwp-6.c: New test.
|
||||
* gcc.target/mips/umips-swp-1.c: New test.
|
||||
* gcc.target/mips/umips-lwp-7.c: New test.
|
||||
* gcc.target/mips/umips-swp-2.c: New test.
|
||||
* gcc.target/mips/umips-lwp-8.c: New test.
|
||||
* gcc.target/mips/umips-swp-3.c: New test.
|
||||
* gcc.target/mips/umips-movep-1.c: New test.
|
||||
* gcc.target/mips/umips-lwp-1.c: New test.
|
||||
* gcc.target/mips/umips-swp-4.c: New test.
|
||||
|
||||
2013-02-24 Catherine Moore <clm@codesourcery.com>
|
||||
Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
|
|
|
|||
|
|
@ -238,7 +238,6 @@ set mips_option_groups {
|
|||
fp "-mfp(32|64)"
|
||||
gp "-mgp(32|64)"
|
||||
long "-mlong(32|64)"
|
||||
micromips "-mmicromips|-mno-micromips"
|
||||
mips16 "-mips16|-mno-mips16|-mflip-mips16"
|
||||
mips3d "-mips3d|-mno-mips3d"
|
||||
pic "-f(no-|)(pic|PIC)"
|
||||
|
|
@ -817,8 +816,6 @@ proc mips-dg-finish {} {
|
|||
# | |
|
||||
# -mips16/-mflip-mips16 -mno-mips16
|
||||
# | |
|
||||
# -micromips -mno-micromips
|
||||
# | |
|
||||
# -mips3d -mno-mips3d
|
||||
# | |
|
||||
# -mpaired-single -mno-paired-single
|
||||
|
|
@ -907,8 +904,6 @@ proc mips-dg-options { args } {
|
|||
|
||||
# Handle dependencies between options on the left of the
|
||||
# dependency diagram.
|
||||
mips_option_dependency options "-mips16" "-mno-micromips"
|
||||
mips_option_dependency options "-mmicromips" "-mno-mips16"
|
||||
mips_option_dependency options "-mips3d" "-mpaired-single"
|
||||
mips_option_dependency options "-mpaired-single" "-mfp64"
|
||||
mips_option_dependency options "-mfp64" "-mhard-float"
|
||||
|
|
@ -1251,10 +1246,6 @@ proc mips-dg-options { args } {
|
|||
append extra_tool_flags " -DMIPS16=__attribute__((mips16))"
|
||||
}
|
||||
|
||||
if { [mips_have_test_option_p options "-mmicromips"] } {
|
||||
append extra_tool_flags " -DMICROMIPS=__attribute__((micromips))"
|
||||
}
|
||||
|
||||
# Use our version of gcc-dg-test for this test.
|
||||
if { ![string equal [info procs "mips-gcc-dg-test"] ""] } {
|
||||
rename gcc-dg-test mips-old-gcc-dg-test
|
||||
|
|
@ -1284,6 +1275,6 @@ proc mips-gcc-dg-test { prog do_what extra_tool_flags } {
|
|||
dg-init
|
||||
mips-dg-init
|
||||
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \
|
||||
"-DNOMIPS16=__attribute__((nomips16)) -DNOMICROMIPS=__attribute__((nomicromips)) -DNOCOMPRESSION=__attribute__((nocompression))"
|
||||
"-DNOMIPS16=__attribute__((nomips16))"
|
||||
mips-dg-finish
|
||||
dg-finish
|
||||
|
|
|
|||
|
|
@ -1,14 +0,0 @@
|
|||
/* { dg-options "(-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
MICROMIPS void
|
||||
foo (int *x)
|
||||
{
|
||||
asm volatile ("insn1\t%a0" :: "ZD" (&x[0]));
|
||||
asm volatile ("insn2\t%a0" :: "ZD" (&x[511]));
|
||||
asm volatile ("insn3\t%a0" :: "ZD" (&x[512]));
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */
|
||||
/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */
|
||||
/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* { dg-options "(-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
MICROMIPS void
|
||||
foo (int *x)
|
||||
{
|
||||
asm volatile ("insn1\t%0" :: "ZC" (x[0]));
|
||||
asm volatile ("insn2\t%0" :: "ZC" (x[511]));
|
||||
asm volatile ("insn3\t%0" :: "ZC" (x[512]));
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */
|
||||
/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */
|
||||
/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4)
|
||||
{
|
||||
int r5 = r4[0];
|
||||
int r6 = r4[1];
|
||||
r4[2] = r5 * r5;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4)
|
||||
{
|
||||
int r5 = r4[0];
|
||||
int r6 = r4[1];
|
||||
r4[2] = r6 * r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4)
|
||||
{
|
||||
int r5 = r4[511];
|
||||
int r6 = r4[512];
|
||||
r4[2] = r5 * r5;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4)
|
||||
{
|
||||
int r5 = r4[511];
|
||||
int r6 = r4[512];
|
||||
r4[2] = r6 * r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4)
|
||||
{
|
||||
int r5 = r4[512];
|
||||
int r6 = r4[513];
|
||||
r4[2] = r5 * r5;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "\tlwp" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4)
|
||||
{
|
||||
int r5 = r4[512];
|
||||
int r6 = r4[513];
|
||||
r4[2] = r6 * r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "\tlwp" } }*/
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
f1 (int *r4, int dummy, int *other)
|
||||
{
|
||||
int r5 = r4[1];
|
||||
int newr4 = r4[0];
|
||||
other[0] = r5 * r5;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r4asm asm ("$4") = newr4;
|
||||
asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm));
|
||||
}
|
||||
}
|
||||
|
||||
void MICROMIPS
|
||||
f2 (int *r4, int dummy, int *other)
|
||||
{
|
||||
int newr4 = r4[0];
|
||||
int r5 = *(int *)(newr4 + 4);
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r4asm asm ("$4") = newr4;
|
||||
asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm));
|
||||
}
|
||||
}
|
||||
|
||||
void MICROMIPS
|
||||
f3 (int dummy, int *r5, int *other)
|
||||
{
|
||||
int newr5 = r5[1];
|
||||
int r4 = *(int *)newr5;
|
||||
{
|
||||
register int r5asm asm ("$4") = r4;
|
||||
register int r4asm asm ("$5") = newr5;
|
||||
asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "\tlwp" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
f1 (int dummy, int *r5, int *other)
|
||||
{
|
||||
int r4 = r5[0];
|
||||
int newr5 = r5[1];
|
||||
other[0] = r4 * r4;
|
||||
{
|
||||
register int r5asm asm ("$4") = r4;
|
||||
register int r4asm asm ("$5") = newr5;
|
||||
asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tlwp\t\\\$4,0\\(\\\$5\\)" } }*/
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mmicromips" } */
|
||||
|
||||
/* This test ensures that we do not generate microMIPS SWP or LWP
|
||||
instructions when any component of the accessed memory is volatile;
|
||||
they are unsafe for such since they might cause replay of partial
|
||||
accesses if interrupted by an exception. */
|
||||
|
||||
static void set_csr (volatile void *p, int v)
|
||||
{
|
||||
*(volatile int *) (p) = v;
|
||||
}
|
||||
|
||||
static int get_csr (volatile void *p)
|
||||
{
|
||||
return *(volatile int *) (p);
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int i, q = 0, p = 0, r = 0;
|
||||
|
||||
for (i = 0; i < 20; i++)
|
||||
{
|
||||
set_csr ((volatile void *) 0xbf0100a8, 0xffff0002);
|
||||
set_csr ((volatile void *) 0xbf0100a4, 0x80000008);
|
||||
}
|
||||
|
||||
for (i = 0; i < 20; i++)
|
||||
{
|
||||
register int k, j;
|
||||
k = get_csr ((volatile void *) 0xbf0100b8);
|
||||
p += k;
|
||||
j = get_csr ((volatile void *) 0xbf0100b4);
|
||||
r += j;
|
||||
q = j + k;
|
||||
}
|
||||
return q + r + p;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "\tswp" } } */
|
||||
/* { dg-final { scan-assembler-not "\tlwp" } } */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/* Check that we can generate the MOVEP instruction. */
|
||||
/* { dg-options "-mgp32 -fpeephole2 (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
long long bar (long long, long long);
|
||||
|
||||
MICROMIPS long long
|
||||
foo (long long n, long long a)
|
||||
{
|
||||
long long i, j;
|
||||
|
||||
i = bar (n, a);
|
||||
j = bar (n, a);
|
||||
return i + j;
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tmovep\t" } } */
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* Check that we can generate the MOVEP instruction. */
|
||||
/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
int bar (int, int);
|
||||
|
||||
int MICROMIPS
|
||||
foo (int n, int a)
|
||||
{
|
||||
return bar (0, 0);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tmovep\t\\\$4,\\\$5,\\\$0,\\\$0" } } */
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
/* Check that we can use the swm/lwm instructions. */
|
||||
/* { dg-options "-mabi=32 (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
int bar (int, int, int, int, int);
|
||||
|
||||
MICROMIPS int
|
||||
foo (int n, int a, int b, int c, int d)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
i = bar (n, a, b, c, d);
|
||||
j = bar (n, a, b, c, d);
|
||||
return i + j;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(0|1),\\\$31" } } */
|
||||
/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(0|1),\\\$31" } } */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/* Check that we can use the save instruction to save spilled arguments. */
|
||||
/* { dg-options "-mabi=32 (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
MICROMIPS void
|
||||
foo (int *a, int b, int c)
|
||||
{
|
||||
asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
|
||||
"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
|
||||
"$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24",
|
||||
"$25", "$30", "memory");
|
||||
a[b] = 1;
|
||||
a[c] = 1;
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$23,\\\$fp" } } */
|
||||
/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$23,\\\$fp" } } */
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* Check that we can use the swm instruction to save $16, $17 and $31. */
|
||||
/* { dg-options "-mgp32 (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void bar (void);
|
||||
|
||||
MICROMIPS void
|
||||
foo (void)
|
||||
{
|
||||
bar ();
|
||||
asm volatile ("" ::: "$16", "$17");
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$17,\\\$31" } } */
|
||||
/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$17,\\\$31" } } */
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (long long l1, long long *l2)
|
||||
{
|
||||
*l2 = l1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tswp\t\\\$4,0\\(\\\$6\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4, int r5, int r6)
|
||||
{
|
||||
r6 *= r6;
|
||||
r4[0] = r5;
|
||||
r4[1] = r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4, int r5, int r6)
|
||||
{
|
||||
r5 *= r5;
|
||||
r4[0] = r5;
|
||||
r4[1] = r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4, int r5, int r6)
|
||||
{
|
||||
r6 *= r6;
|
||||
r4[511] = r5;
|
||||
r4[512] = r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4, int r5, int r6)
|
||||
{
|
||||
r5 *= r5;
|
||||
r4[511] = r5;
|
||||
r4[512] = r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4, int r5, int r6)
|
||||
{
|
||||
r6 *= r6;
|
||||
r4[512] = r5;
|
||||
r4[513] = r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "\tswp" } }*/
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
|
||||
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
|
||||
|
||||
void MICROMIPS
|
||||
foo (int *r4, int r5, int r6)
|
||||
{
|
||||
r5 *= r5;
|
||||
r4[512] = r5;
|
||||
r4[513] = r6;
|
||||
{
|
||||
register int r5asm asm ("$5") = r5;
|
||||
register int r6asm asm ("$6") = r6;
|
||||
asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
|
||||
}
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "\tswp" } }*/
|
||||
|
|
@ -1,3 +1,14 @@
|
|||
2013-02-25 Catherine Moore <clm@codesourcery.com>
|
||||
|
||||
Revert:
|
||||
2013-02-24 Catherine Moore <clm@codesourcery.com>
|
||||
Joseph Myers <joseph@codesourcery.com>
|
||||
Chao-ying Fu <fu@mips.com>
|
||||
|
||||
* config/mips/mips16.S: Don't build for microMIPS.
|
||||
* config/mips/linux-unwind.h: Handle microMIPS frame.
|
||||
* config/mips/crtn.S (fini, init): New labels.
|
||||
|
||||
2013-02-24 Catherine Moore <clm@codesourcery.com>
|
||||
Joseph Myers <joseph@codesourcery.com>
|
||||
Chao-ying Fu <fu@mips.com>
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
|||
#endif
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
init:
|
||||
#ifdef __mips64
|
||||
ld RA,40($sp)
|
||||
daddu $sp,$sp,48
|
||||
|
|
@ -42,7 +41,6 @@ init:
|
|||
j RA
|
||||
|
||||
.section .fini,"ax",@progbits
|
||||
fini:
|
||||
#ifdef __mips64
|
||||
ld RA,40($sp)
|
||||
daddu $sp,$sp,48
|
||||
|
|
|
|||
|
|
@ -51,11 +51,6 @@ mips_fallback_frame_state (struct _Unwind_Context *context,
|
|||
_Unwind_Ptr new_cfa, reg_offset;
|
||||
int i;
|
||||
|
||||
/* A MIPS16 or microMIPS frame. Signal frames always use the standard
|
||||
ISA encoding. */
|
||||
if ((_Unwind_Ptr) pc & 3)
|
||||
return _URC_END_OF_STACK;
|
||||
|
||||
/* 24021061 li v0, 0x1061 (rt_sigreturn)*/
|
||||
/* 0000000c syscall */
|
||||
/* or */
|
||||
|
|
|
|||
|
|
@ -21,10 +21,6 @@ a copy of the GCC Runtime Library Exception along with this program;
|
|||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifdef __mips_micromips
|
||||
/* DO NOTHING */
|
||||
#else
|
||||
|
||||
/* This file contains mips16 floating point support functions. These
|
||||
functions are called by mips16 code to handle floating point when
|
||||
-msoft-float is not used. They accept the arguments and return
|
||||
|
|
@ -722,4 +718,3 @@ CALL_STUB_RET (__mips16_call_stub_dc_10, 10, DC)
|
|||
#endif /* !__mips_single_float */
|
||||
|
||||
#endif
|
||||
#endif /* __mips_micromips */
|
||||
|
|
|
|||
Loading…
Reference in New Issue