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* x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+.

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From-SVN: r254343
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Jan Hubicka 2017-11-02 14:49:31 +01:00 committed by Jan Hubicka
parent 1e8fc1ce6e
commit 6d7e169ebd
2 changed files with 12 additions and 3 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2017-11-02 Jan Hubicka <hubicka@ucw.cz>
* x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+.
2017-11-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/82795

11
gcc/config/i386/x86-tune.def
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@ -220,10 +220,15 @@ DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
as "add mem, reg". */
DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */
/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
Core2 and nehalem has stall of 7 cycles for partial flag register stalls.
Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop
is output only when the values needs to be really merged, which is not
done by GCC generated code. */
DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_KNM | m_GENERIC))
~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GENERIC))
/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
for DFmode copies */