i386.md (absneg): New code iterator.
* config/i386/i386.md (absneg): New code iterator. (absnegprefix): New code attribute. (<code><mode>2): Macroize expander from abs<mode>2 and neg<mode>2 patterns using absneg code iterator. (<code>tf2): Macroize expander from abstf2 and negtf2 patterns using absneg code iterator. (*<code><mode>2_1): Macroize insn pattern from *abs<mode>2_1 and *neg<mode>2 patterns using absneg code iterator. (*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and *negextendsfdf2 patterns using absneg code iterator. (*<code>extendsfxf2): Macroize insn pattern from *absextendsfxf2 and *negextendsfxf2 patterns using absneg code iterator. (*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and *negextendsfdf2 patterns using absneg code iterator. * config/i386/sse.md (<code><mode>2): Macroize expander from abs<mode>2 and neg<mode>2 patterns using absneg code iterator. From-SVN: r134165
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2008-04-10 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (absneg): New code iterator.
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(absnegprefix): New code attribute.
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(<code><mode>2): Macroize expander from abs<mode>2 and neg<mode>2
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patterns using absneg code iterator.
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(<code>tf2): Macroize expander from abstf2 and negtf2 patterns
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using absneg code iterator.
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(*<code><mode>2_1): Macroize insn pattern from *abs<mode>2_1 and
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*neg<mode>2 patterns using absneg code iterator.
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(*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and
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*negextendsfdf2 patterns using absneg code iterator.
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(*<code>extendsfxf2): Macroize insn pattern from *absextendsfxf2 and
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*negextendsfxf2 patterns using absneg code iterator.
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(*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and
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*negextendsfdf2 patterns using absneg code iterator.
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* config/i386/sse.md (<code><mode>2): Macroize expander from
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abs<mode>2 and neg<mode>2 patterns using absneg code iterator.
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2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
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2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
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* config/s390/s390.h: Remove the remains of the recent search
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* config/s390/s390.h: Remove the remains of the recent search
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@ -548,7 +548,8 @@
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(define_code_iterator umaxmin [umax umin])
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(define_code_iterator umaxmin [umax umin])
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;; Base name for integer and FP insn mnemonic
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;; Base name for integer and FP insn mnemonic
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(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
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(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
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(umax "maxu") (umin "minu")])
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(define_code_attr maxminfprefix [(smax "max") (smin "min")])
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(define_code_attr maxminfprefix [(smax "max") (smin "min")])
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;; Mapping of parallel logic operators
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;; Mapping of parallel logic operators
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@ -557,6 +558,12 @@
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;; Base name for insn mnemonic.
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;; Base name for insn mnemonic.
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(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
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(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
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;; Mapping of abs neg operators
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(define_code_iterator absneg [abs neg])
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;; Base name for x87 insn mnemonic.
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(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
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;; All single word integer modes.
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;; All single word integer modes.
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(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
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(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
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@ -10379,17 +10386,11 @@
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;; Changing of sign for FP values is doable using integer unit too.
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;; Changing of sign for FP values is doable using integer unit too.
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(define_expand "neg<mode>2"
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(define_expand "<code><mode>2"
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[(set (match_operand:X87MODEF 0 "register_operand" "")
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[(set (match_operand:X87MODEF 0 "register_operand" "")
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(neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
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(absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;")
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"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
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(define_expand "abs<mode>2"
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[(set (match_operand:X87MODEF 0 "register_operand" "")
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(abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
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(define_insn "*absneg<mode>2_mixed"
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(define_insn "*absneg<mode>2_mixed"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
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@ -10418,17 +10419,11 @@
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"TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"#")
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"#")
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(define_expand "negtf2"
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(define_expand "<code>tf2"
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[(set (match_operand:TF 0 "register_operand" "")
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[(set (match_operand:TF 0 "register_operand" "")
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(neg:TF (match_operand:TF 1 "register_operand" "")))]
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(absneg:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_64BIT"
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"TARGET_64BIT"
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"ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;")
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"ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
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(define_expand "abstf2"
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[(set (match_operand:TF 0 "register_operand" "")
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(abs:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_64BIT"
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"ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;")
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(define_insn "*absnegtf2_sse"
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(define_insn "*absnegtf2_sse"
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[(set (match_operand:TF 0 "register_operand" "=x,x")
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[(set (match_operand:TF 0 "register_operand" "=x,x")
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@ -10568,75 +10563,40 @@
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;; Conditionalize these after reload. If they match before reload, we
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;; Conditionalize these after reload. If they match before reload, we
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;; lose the clobber and ability to use integer instructions.
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;; lose the clobber and ability to use integer instructions.
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(define_insn "*neg<mode>2_1"
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(define_insn "*<code><mode>2_1"
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[(set (match_operand:X87MODEF 0 "register_operand" "=f")
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[(set (match_operand:X87MODEF 0 "register_operand" "=f")
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(neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
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(absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
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"TARGET_80387
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"TARGET_80387
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&& (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
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&& (reload_completed
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"fchs"
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|| !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
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"f<absnegprefix>"
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[(set_attr "type" "fsgn")
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[(set_attr "type" "fsgn")
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(set_attr "mode" "<MODE>")])
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(set_attr "mode" "<MODE>")])
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(define_insn "*abs<mode>2_1"
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(define_insn "*<code>extendsfdf2"
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[(set (match_operand:X87MODEF 0 "register_operand" "=f")
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(abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
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"TARGET_80387
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&& (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
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"fabs"
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[(set_attr "type" "fsgn")
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(set_attr "mode" "<MODE>")])
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(define_insn "*negextendsfdf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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[(set (match_operand:DF 0 "register_operand" "=f")
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(neg:DF (float_extend:DF
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(absneg:DF (float_extend:DF
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(match_operand:SF 1 "register_operand" "0"))))]
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(match_operand:SF 1 "register_operand" "0"))))]
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"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
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"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
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"fchs"
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"f<absnegprefix>"
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[(set_attr "type" "fsgn")
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[(set_attr "type" "fsgn")
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(set_attr "mode" "DF")])
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(set_attr "mode" "DF")])
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(define_insn "*negextenddfxf2"
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(define_insn "*<code>extendsfxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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[(set (match_operand:XF 0 "register_operand" "=f")
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(neg:XF (float_extend:XF
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(absneg:XF (float_extend:XF
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(match_operand:DF 1 "register_operand" "0"))))]
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(match_operand:SF 1 "register_operand" "0"))))]
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"TARGET_80387"
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"TARGET_80387"
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"fchs"
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"f<absnegprefix>"
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[(set_attr "type" "fsgn")
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[(set_attr "type" "fsgn")
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(set_attr "mode" "XF")])
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(set_attr "mode" "XF")])
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(define_insn "*negextendsfxf2"
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(define_insn "*<code>extenddfxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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[(set (match_operand:XF 0 "register_operand" "=f")
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(neg:XF (float_extend:XF
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(absneg:XF (float_extend:XF
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(match_operand:SF 1 "register_operand" "0"))))]
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(match_operand:DF 1 "register_operand" "0"))))]
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"TARGET_80387"
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"TARGET_80387"
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"fchs"
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"f<absnegprefix>"
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[(set_attr "type" "fsgn")
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(set_attr "mode" "XF")])
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(define_insn "*absextendsfdf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(abs:DF (float_extend:DF
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(match_operand:SF 1 "register_operand" "0"))))]
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"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
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"fabs"
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[(set_attr "type" "fsgn")
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(set_attr "mode" "DF")])
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(define_insn "*absextenddfxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(abs:XF (float_extend:XF
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(match_operand:DF 1 "register_operand" "0"))))]
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"TARGET_80387"
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"fabs"
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[(set_attr "type" "fsgn")
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(set_attr "mode" "XF")])
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(define_insn "*absextendsfxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(abs:XF (float_extend:XF
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(match_operand:SF 1 "register_operand" "0"))))]
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"TARGET_80387"
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"fabs"
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[(set_attr "type" "fsgn")
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[(set_attr "type" "fsgn")
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(set_attr "mode" "XF")])
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(set_attr "mode" "XF")])
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(define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
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(define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
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;; Mapping of the sse5 suffix
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;; Mapping of the sse5 suffix
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(define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd") (V4SF "ps") (V2DF "pd")])
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(define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd")
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(define_mode_attr ssemodesuffixf2s [(SF "ss") (DF "sd") (V4SF "ss") (V2DF "sd")])
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(V4SF "ps") (V2DF "pd")])
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(define_mode_attr ssemodesuffixf2s [(SF "ss") (DF "sd")
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(V4SF "ss") (V2DF "sd")])
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(define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")])
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(define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")])
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;; Mapping of the max integer size for sse5 rotate immediate constraint
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;; Mapping of the max integer size for sse5 rotate immediate constraint
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;;
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "neg<mode>2"
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(define_expand "<code><mode>2"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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(neg:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "")))]
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(absneg:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "register_operand" "")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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"ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;")
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"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
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(define_expand "abs<mode>2"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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(abs:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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"ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
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(define_expand "<addsub><mode>3"
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(define_expand "<addsub><mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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