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[AArch64] Fix FAIL: gcc.target/aarch64/target_attr_crypto_ice_1.c (internal compiler error)

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* config/aarch64/aarch64.c (aarch64_set_current_function):
	Re-layout any vector parameters have non-simd layout.
	* config/aarch64/aarch64-builtins.c (aarch64_relayout_simd_param):
	Delete.
	(aarch64_simd_expand_args): Delete call to the above.

	* gcc.target/aarch64/target_attr_crypto_ice_2.c: New test.

From-SVN: r227363
This commit is contained in:
Kyrylo Tkachov 2015-09-01 10:32:24 +00:00 committed by Kyrylo Tkachov
parent 6853b04cdd
commit 6e17a23b53
5 changed files with 49 additions and 25 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2015-09-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_set_current_function):
Re-layout any vector parameters have non-simd layout.
* config/aarch64/aarch64-builtins.c (aarch64_relayout_simd_param):
Delete.
(aarch64_simd_expand_args): Delete call to the above.
2015-08-31 Mike Frysinger <vapier@gentoo.org>
* doc/invoke.texi (asan-stack): Add space before option.

25
gcc/config/aarch64/aarch64-builtins.c
View File

@ -886,30 +886,6 @@ typedef enum
SIMD_ARG_STOP
} builtin_simd_arg;
/* Relayout the decl of a function arg. Keep the RTL component the same,
as varasm.c ICEs. It doesn't like reinitializing the RTL
on PARM decls. Something like this needs to be done when compiling a
file without SIMD and then tagging a function with +simd and using SIMD
intrinsics in there. The types will have been laid out assuming no SIMD,
so we want to re-lay them out. */
static void
aarch64_relayout_simd_param (tree arg)
{
tree argdecl = arg;
if (TREE_CODE (argdecl) == SSA_NAME)
argdecl = SSA_NAME_VAR (argdecl);
if (argdecl
&& (TREE_CODE (argdecl) == PARM_DECL
|| TREE_CODE (argdecl) == VAR_DECL))
{
rtx rtl = NULL_RTX;
rtl = DECL_RTL_IF_SET (argdecl);
relayout_decl (argdecl);
SET_DECL_RTL (argdecl, rtl);
}
}
static rtx
aarch64_simd_expand_args (rtx target, int icode, int have_retval,
@ -940,7 +916,6 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
{
tree arg = CALL_EXPR_ARG (exp, opc - have_retval);
enum machine_mode mode = insn_data[icode].operand[opc].mode;
aarch64_relayout_simd_param (arg);
op[opc] = expand_normal (arg);
switch (thisarg)

17
gcc/config/aarch64/aarch64.c
View File

@ -8111,6 +8111,23 @@ aarch64_set_current_function (tree fndecl)
= save_target_globals_default_opts ();
}
}
if (!fndecl)
return;
/* If we turned on SIMD make sure that any vector parameters are re-laid out
so that they use proper vector modes. */
if (TARGET_SIMD)
{
tree parms = DECL_ARGUMENTS (fndecl);
for (; parms && parms != void_list_node; parms = TREE_CHAIN (parms))
{
if (TREE_CODE (parms) == PARM_DECL
&& VECTOR_TYPE_P (TREE_TYPE (parms))
&& DECL_MODE (parms) != TYPE_MODE (TREE_TYPE (parms)))
relayout_decl (parms);
}
}
}
/* Enum describing the various ways we can handle attributes.

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2015-09-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/target_attr_crypto_ice_2.c: New test.
2015-09-01 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/61753

20
gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c Normal file
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@ -0,0 +1,20 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
/* Make sure that we don't ICE when dealing with vector parameters
in a simd-tagged function within a non-simd translation unit. */
#pragma GCC push_options
#pragma GCC target ("+nothing+simd")
typedef unsigned int __uint32_t;
typedef __uint32_t uint32_t ;
typedef __Uint32x4_t uint32x4_t;
#pragma GCC pop_options
__attribute__ ((target ("cpu=cortex-a57")))
uint32x4_t
foo (uint32x4_t a, uint32_t b, uint32x4_t c)
{
return c;
}