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[AARCH64][Insn classification unification 3/N] ALU/shift types 

2013-09-05  James Greenhalgh  <james.greenhalgh@arm.com>
	    Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/types.md (define_attr "type"):
	Expand "arlo_imm"
	into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
	Expand "arlo_reg"
	into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
	"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
	"logics_reg", "rev".
	Expand "arlo_shift"
	into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
	"logics_shift_imm".
	Expand "arlo_shift_reg"
	into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
	"logics_shift_reg".
	Expand "clz" into "clz, "rbit".
	Rename "shift" to "shift_imm".
	* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
	changes.
	Update for attribute changes all occurrences of arlo_* and
	shift* types.
	* config/arm/arm-fixed.md: Update for attribute changes
	all occurrences of arlo_* types.
	* config/arm/thumb2.md: Update for attribute changes all occurrences
	of arlo_* types.
	* config/arm/arm.c (xscale_sched_adjust_cost):  (rtx insn, rtx
	(cortexa7_older_only): Likewise.
	(cortexa7_younger):  Likewise.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for
	attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for
	attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for
	attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md
	(cortex_a53_alu): Update for attribute changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md
	(cortex_a7_alu_imm): Update for attribute changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md
	(cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	* config/arm/cortex-a9.md
	(cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md
	(cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md
	(cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md
	(526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md
	(606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md
	(626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md
	(726te_alu_op): Update for attribute changes.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/aarch64/aarch64.md: Update for attribute change
	all occurrences of arlo_* and shift* types.



Co-Authored-By: Sofiane Naci <sofiane.naci@arm.com>

From-SVN: r202291
This commit is contained in:
James Greenhalgh 2013-09-05 15:49:15 +00:00 committed by James Greenhalgh
parent 7c812a2a57
commit 6e4150e1d4
25 changed files with 619 additions and 299 deletions
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91
gcc/ChangeLog
View File

@ -1,3 +1,94 @@
2013-09-05 James Greenhalgh <james.greenhalgh@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
* config/arm/types.md (define_attr "type"):
Expand "arlo_imm"
into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
Expand "arlo_reg"
into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
"logics_reg", "rev".
Expand "arlo_shift"
into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
"logics_shift_imm".
Expand "arlo_shift_reg"
into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
"logics_shift_reg".
Expand "clz" into "clz, "rbit".
Rename "shift" to "shift_imm".
* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
changes.
Update for attribute changes all occurrences of arlo_* and
shift* types.
* config/arm/arm-fixed.md: Update for attribute changes
all occurrences of arlo_* types.
* config/arm/thumb2.md: Update for attribute changes all occurrences
of arlo_* types.
* config/arm/arm.c (xscale_sched_adjust_cost): (rtx insn, rtx
(cortexa7_older_only): Likewise.
(cortexa7_younger): Likewise.
* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
(1020alu_shift_op): Likewise.
(1020alu_shift_reg_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
(alu_shift_op): Likewise.
(alu_shift_reg_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Update for
attribute changes.
(11_alu_shift_op): Likewise.
(11_alu_shift_reg_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
(9_alu_shift_reg_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Update for
attribute changes.
(cortex_a15_alu_shift): Likewise.
(cortex_a15_alu_shift_reg): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Update for
attribute changes.
(cortex_a5_alu_shift): Likewise.
* config/arm/cortex-a53.md
(cortex_a53_alu): Update for attribute changes.
(cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a7.md
(cortex_a7_alu_imm): Update for attribute changes.
(cortex_a7_alu_reg): Likewise.
(cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md
(cortex_a8_alu): Update for attribute changes.
(cortex_a8_alu_shift): Likewise.
(cortex_a8_alu_shift_reg): Likewise.
* config/arm/cortex-a9.md
(cortex_a9_dp): Update for attribute changes.
(cortex_a9_dp_shift): Likewise.
* config/arm/cortex-m4.md
(cortex_m4_alu): Update for attribute changes.
* config/arm/cortex-r4.md
(cortex_r4_alu): Update for attribute changes.
(cortex_r4_mov): Likewise.
(cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md
(526_alu_op): Update for attribute changes.
(526_alu_shift_op): Likewise.
* config/arm/fa606te.md
(606te_alu_op): Update for attribute changes.
* config/arm/fa626te.md
(626te_alu_op): Update for attribute changes.
(626te_alu_shift_op): Likewise.
* config/arm/fa726te.md
(726te_alu_op): Update for attribute changes.
(726te_alu_shift_op): Likewise.
(726te_alu_shift_reg_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
(mp626_alu_shift_op): Likewise.
* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
(pj4_alu_conds): Likewise.
(pj4_shift): Likewise.
(pj4_shift_conds): Likewise.
(pj4_alu_shift): Likewise.
(pj4_alu_shift_conds): Likewise.
* config/aarch64/aarch64.md: Update for attribute change
all occurrences of arlo_* and shift* types.
2013-09-05 Mike Stump <mikestump@comcast.net>
* tree.h: Move documentation for tree_function_decl to tree-core.h

254
gcc/config/aarch64/aarch64.md
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File diff suppressed because it is too large Load Diff

2
gcc/config/arm/arm-fixed.md
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@ -406,7 +406,7 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
(set_attr "type" "arlo_shift")])
(set_attr "type" "alu_shift_imm")])
(define_insn "arm_usatsihi"
[(set (match_operand:HI 0 "s_register_operand" "=r")

27
gcc/config/arm/arm.c
View File

@ -8664,8 +8664,14 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
instruction we depend on is another ALU instruction, then we may
have to account for an additional stall. */
if (shift_opnum != 0
&& (attr_type == TYPE_ARLO_SHIFT
|| attr_type == TYPE_ARLO_SHIFT_REG
&& (attr_type == TYPE_ALU_SHIFT_IMM
|| attr_type == TYPE_ALUS_SHIFT_IMM
|| attr_type == TYPE_LOGIC_SHIFT_IMM
|| attr_type == TYPE_LOGICS_SHIFT_IMM
|| attr_type == TYPE_ALU_SHIFT_REG
|| attr_type == TYPE_ALUS_SHIFT_REG
|| attr_type == TYPE_LOGIC_SHIFT_REG
|| attr_type == TYPE_LOGICS_SHIFT_REG
|| attr_type == TYPE_MOV_SHIFT
|| attr_type == TYPE_MVN_SHIFT
|| attr_type == TYPE_MOV_SHIFT_REG
@ -8952,9 +8958,17 @@ cortexa7_older_only (rtx insn)
switch (get_attr_type (insn))
{
case TYPE_ARLO_REG:
case TYPE_ALU_REG:
case TYPE_ALUS_REG:
case TYPE_LOGIC_REG:
case TYPE_LOGICS_REG:
case TYPE_ADC_REG:
case TYPE_ADCS_REG:
case TYPE_ADR:
case TYPE_BFM:
case TYPE_REV:
case TYPE_MVN_REG:
case TYPE_SHIFT:
case TYPE_SHIFT_IMM:
case TYPE_SHIFT_REG:
case TYPE_LOAD_BYTE:
case TYPE_LOAD1:
@ -8999,7 +9013,10 @@ cortexa7_younger (FILE *file, int verbose, rtx insn)
switch (get_attr_type (insn))
{
case TYPE_ARLO_IMM:
case TYPE_ALU_IMM:
case TYPE_ALUS_IMM:
case TYPE_LOGIC_IMM:
case TYPE_LOGICS_IMM:
case TYPE_EXTEND:
case TYPE_MVN_IMM:
case TYPE_MOV_IMM:

192
gcc/config/arm/arm.md
View File

@ -330,8 +330,12 @@
; than one on the main cpu execution unit.
(define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type"
"arlo_imm, arlo_reg,\
extend, shift, arlo_shift, float, fdivd, fdivs,\
"adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\
alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\
alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
fdivd, fdivs,\
wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
@ -616,8 +620,8 @@
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "arlo_imm")
(const_string "arlo_reg")))
(const_string "alu_imm")
(const_string "alu_reg")))
]
)
@ -698,7 +702,7 @@
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,arlo_imm,*")]
(set_attr "type" "alus_imm,alus_imm,*")]
)
(define_insn "*addsi3_compare0_scratch"
@ -714,7 +718,7 @@
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "type" "arlo_imm,arlo_imm,*")
(set_attr "type" "alus_imm,alus_imm,*")
]
)
@ -804,7 +808,7 @@
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,arlo_imm,*")]
(set_attr "type" "alus_imm,alus_imm,alus_reg")]
)
(define_insn "*addsi3_compare_op2"
@ -821,7 +825,7 @@
add%.\\t%0, %1, %2
sub%.\\t%0, %1, #%n2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,arlo_imm,*")]
(set_attr "type" "alus_imm,alus_imm,alus_reg")]
)
(define_insn "*compare_addsi2_op0"
@ -842,7 +846,7 @@
(set_attr "arch" "t2,t2,*,*,*")
(set_attr "predicable_short_it" "yes,yes,no,no,no")
(set_attr "length" "2,2,4,4,4")
(set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")]
(set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")]
)
(define_insn "*compare_addsi2_op1"
@ -863,8 +867,7 @@
(set_attr "arch" "t2,t2,*,*,*")
(set_attr "predicable_short_it" "yes,yes,no,no,no")
(set_attr "length" "2,2,4,4,4")
(set_attr "type"
"arlo_imm,*,arlo_imm,arlo_imm,*")]
(set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")]
)
(define_insn "*addsi3_carryin_<optab>"
@ -915,8 +918,8 @@
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
(const_string "alu_shift_imm")
(const_string "alu_shift_reg")))]
)
(define_insn "*addsi3_carryin_clobercc_<optab>"
@ -994,8 +997,8 @@
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
(const_string "alu_shift_imm")
(const_string "alu_shift_reg")))]
)
(define_insn "*rsbsi3_carryin_shift"
@ -1011,8 +1014,8 @@
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
(const_string "alu_shift_imm")
(const_string "alu_shift_reg")))]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
@ -1285,7 +1288,7 @@
(set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
(set_attr "type" "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")]
(set_attr "type" "*,*,*,*,alu_imm,alu_imm,*,*,alu_imm")]
)
(define_peephole2
@ -1315,7 +1318,7 @@
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,*,*")]
(set_attr "type" "alus_imm,alus_reg,alus_reg")]
)
(define_insn "subsi3_compare"
@ -1330,7 +1333,7 @@
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,*,*")]
(set_attr "type" "alus_imm,alus_reg,alus_reg")]
)
(define_expand "subsf3"
@ -2279,8 +2282,7 @@
[(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type"
"arlo_imm,arlo_imm,*,*,arlo_imm")]
(set_attr "type" "logic_imm,logic_imm,logic_reg,logic_reg,logic_imm")]
)
(define_insn "*thumb1_andsi3_insn"
@ -2290,7 +2292,7 @@
"TARGET_THUMB1"
"and\\t%0, %2"
[(set_attr "length" "2")
(set_attr "type" "arlo_imm")
(set_attr "type" "logic_imm")
(set_attr "conds" "set")])
(define_insn "*andsi3_compare0"
@ -2307,7 +2309,7 @@
bic%.\\t%0, %1, #%B2
and%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,arlo_imm,*")]
(set_attr "type" "logics_imm,logics_imm,logics_reg")]
)
(define_insn "*andsi3_compare0_scratch"
@ -2323,7 +2325,7 @@
bic%.\\t%2, %0, #%B1
tst%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,arlo_imm,*")]
(set_attr "type" "logics_imm,logics_imm,logics_reg")]
)
(define_insn "*zeroextractsi_compare0_scratch"
@ -2347,7 +2349,7 @@
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "arlo_imm")]
(set_attr "type" "logics_imm")]
)
(define_insn_and_split "*ne_zeroextractsi"
@ -2775,7 +2777,8 @@
"bfc%?\t%0, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
(define_insn "insv_t2"
@ -2787,7 +2790,8 @@
"bfi%?\t%0, %3, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
; constants for op 2 will never be given to these patterns.
@ -2897,8 +2901,8 @@
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
(const_string "logic_shift_imm")
(const_string "logic_shift_reg")))]
)
(define_insn "*andsi_notsi_si_compare0"
@ -2911,7 +2915,8 @@
(and:SI (not:SI (match_dup 2)) (match_dup 1)))]
"TARGET_32BIT"
"bic%.\\t%0, %1, %2"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "type" "logics_shift_reg")]
)
(define_insn "*andsi_notsi_si_compare0_scratch"
@ -2923,7 +2928,8 @@
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_32BIT"
"bic%.\\t%0, %1, %2"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "type" "logics_shift_reg")]
)
(define_expand "iordi3"
@ -3057,7 +3063,7 @@
(set_attr "arch" "32,t2,t2,32,32")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type" "arlo_imm,*,arlo_imm,*,*")]
(set_attr "type" "logic_imm,logic_reg,logic_imm,logic_reg,logic_reg")]
)
(define_insn "*thumb1_iorsi3_insn"
@ -3092,7 +3098,7 @@
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,*")]
(set_attr "type" "logics_imm,logics_reg")]
)
(define_insn "*iorsi3_compare0_scratch"
@ -3104,7 +3110,7 @@
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,*")]
(set_attr "type" "logics_imm,logics_reg")]
)
(define_expand "xordi3"
@ -3230,7 +3236,7 @@
[(set_attr "length" "4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no")
(set_attr "type" "arlo_imm,*,*,*")]
(set_attr "type" "logic_imm,logic_reg,logic_reg,logic_reg")]
)
(define_insn "*thumb1_xorsi3_insn"
@ -3241,7 +3247,7 @@
"eor\\t%0, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
(set_attr "type" "arlo_imm")]
(set_attr "type" "logics_reg")]
)
(define_insn "*xorsi3_compare0"
@ -3254,7 +3260,7 @@
"TARGET_32BIT"
"eor%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,*")]
(set_attr "type" "logics_imm,logics_reg")]
)
(define_insn "*xorsi3_compare0_scratch"
@ -3265,7 +3271,7 @@
"TARGET_32BIT"
"teq%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,*")]
(set_attr "type" "logics_imm,logics_reg")]
)
; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
@ -3754,7 +3760,7 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "3")
(set_attr "type" "arlo_shift")])
(set_attr "type" "logic_shift_reg")])
;; Shift and rotation insns
@ -3857,7 +3863,7 @@
"TARGET_THUMB1"
"lsl\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift,shift_reg")
(set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
(define_expand "ashrdi3"
@ -3962,7 +3968,7 @@
"TARGET_THUMB1"
"asr\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift,shift_reg")
(set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
(define_expand "lshrdi3"
@ -4059,7 +4065,7 @@
"TARGET_THUMB1"
"lsr\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift,shift_reg")
(set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
(define_expand "rotlsi3"
@ -4121,7 +4127,7 @@
(set_attr "predicable_short_it" "yes,no,no")
(set_attr "length" "4")
(set_attr "shift" "1")
(set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")]
(set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_reg")]
)
(define_insn "*shiftsi3_compare"
@ -4136,7 +4142,7 @@
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "arlo_shift,arlo_shift_reg")]
(set_attr "type" "alus_shift_imm,alus_shift_reg")]
)
(define_insn "*shiftsi3_compare0"
@ -4151,7 +4157,7 @@
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "arlo_shift,arlo_shift_reg")]
(set_attr "type" "alus_shift_imm,alus_shift_reg")]
)
(define_insn "*shiftsi3_compare0_scratch"
@ -4165,7 +4171,7 @@
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "shift,shift_reg")]
(set_attr "type" "shift_imm,shift_reg")]
)
(define_insn "*not_shiftsi"
@ -4507,7 +4513,8 @@
"sbfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
(define_insn "extzv_t2"
@ -4519,7 +4526,8 @@
"ubfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
@ -5241,7 +5249,7 @@
"@
#
ldr%(h%)\\t%0, %1"
[(set_attr "type" "arlo_shift,load_byte")
[(set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")]
)
@ -5262,7 +5270,7 @@
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"uxtah%?\\t%0, %2, %1"
[(set_attr "type" "arlo_shift")
[(set_attr "type" "alu_shift_reg")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
)
@ -5312,7 +5320,7 @@
#
ldrb\\t%0, %1"
[(set_attr "length" "4,2")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "type" "alu_shift_reg,load_byte")
(set_attr "pool_range" "*,32")]
)
@ -5335,7 +5343,7 @@
#
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "length" "8,4")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")]
)
@ -5358,7 +5366,7 @@
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "arlo_shift")]
(set_attr "type" "alu_shift_reg")]
)
(define_split
@ -5580,7 +5588,7 @@
#
ldr%(sh%)\\t%0, %1"
[(set_attr "length" "8,4")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@ -5681,7 +5689,7 @@
#
ldr%(sb%)\\t%0, %1"
[(set_attr "length" "8,4")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@ -5707,7 +5715,7 @@
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "arlo_shift")
[(set_attr "type" "alu_shift_reg")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
)
@ -6484,7 +6492,7 @@
cmp%?\\t%0, #0
sub%.\\t%0, %1, #0"
[(set_attr "conds" "set")
(set_attr "type" "arlo_imm,arlo_imm")]
(set_attr "type" "alus_imm,alus_imm")]
)
;; Subroutine to store a half word from a register into memory.
@ -7078,7 +7086,7 @@
mov\\t%0, %1
mov\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "arlo_imm,load1,store1,mov_reg,mov_imm,mov_imm")
(set_attr "type" "alu_imm,load1,store1,mov_reg,mov_imm,mov_imm")
(set_attr "pool_range" "*,32,*,*,*,*")
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
@ -8164,34 +8172,34 @@
(set_attr "arch" "t2,t2,any,any")
(set_attr "length" "2,2,4,4")
(set_attr "predicable" "yes")
(set_attr "type" "*,*,*,arlo_imm")]
(set_attr "type" "alus_reg,alus_reg,alus_reg,alus_imm")]
)
(define_insn "*cmpsi_shiftsi"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
(compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
[(match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
"TARGET_32BIT"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "arch" "32,a,a")
(set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")])
(define_insn "*cmpsi_shiftsi_swp"
[(set (reg:CC_SWP CC_REGNUM)
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "shift_amount_operand" "M,rM")])
(match_operand:SI 0 "s_register_operand" "r,r")))]
[(match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "shift_amount_operand" "M,r,M")])
(match_operand:SI 0 "s_register_operand" "r,r,r")))]
"TARGET_32BIT"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "arch" "32,a,a")
(set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")])
(define_insn "*arm_cmpsi_negshiftsi_si"
[(set (reg:CC_Z CC_REGNUM)
@ -8204,8 +8212,8 @@
"cmn%?\\t%0, %2%S1"
[(set_attr "conds" "set")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))
(const_string "alus_shift_imm")
(const_string "alus_shift_reg")))
(set_attr "predicable" "yes")]
)
@ -9747,7 +9755,7 @@
(if_then_else
(match_operand:SI 3 "mult_operator" "")
(const_string "no") (const_string "yes"))])
(set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")])
(set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_imm,alu_shift_reg")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
@ -9784,7 +9792,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*arith_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
@ -9801,7 +9809,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@ -9814,41 +9822,41 @@
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r,r")
(match_operand:SI 4 "shift_amount_operand" "M,rM")]))
[(match_operand:SI 3 "s_register_operand" "r,r,r")
(match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(minus:SI (match_dup 1)
(match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
"TARGET_32BIT"
"sub%.\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "arch" "32,a,a")
(set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
(define_insn "*sub_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r,r")
(match_operand:SI 4 "shift_amount_operand" "M,rM")]))
[(match_operand:SI 3 "s_register_operand" "r,r,r")
(match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r,r"))]
(clobber (match_scratch:SI 0 "=r,r,r"))]
"TARGET_32BIT"
"sub%.\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(set_attr "arch" "32,a,a")
(set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
(define_insn_and_split "*and_scc"
@ -10900,9 +10908,9 @@
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
(const_string "arlo_imm" )
(const_string "alu_imm" )
(const_string "*"))
(const_string "arlo_imm")
(const_string "alu_imm")
(const_string "*")
(const_string "*")])]
)
@ -10942,9 +10950,9 @@
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
(const_string "arlo_imm" )
(const_string "alu_imm" )
(const_string "*"))
(const_string "arlo_imm")
(const_string "alu_imm")
(const_string "*")
(const_string "*")])]
)

14
gcc/config/arm/arm1020e.md
View File

@ -66,14 +66,20 @@
;; ALU operations with no shifted operand
(define_insn_reservation "1020alu_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "1020alu_shift_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-register operand
@ -82,7 +88,9 @@
;; the execute stage.
(define_insn_reservation "1020alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg"))
"1020a_e*2,1020a_m,1020a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

14
gcc/config/arm/arm1026ejs.md
View File

@ -66,14 +66,20 @@
;; ALU operations with no shifted operand
(define_insn_reservation "alu_op" 1
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "alu_shift_op" 1
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-register operand
@ -82,7 +88,9 @@
;; the execute stage.
(define_insn_reservation "alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg"))
"a_e*2,a_m,a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

14
gcc/config/arm/arm1136jfs.md
View File

@ -75,14 +75,20 @@
;; ALU operations with no shifted operand
(define_insn_reservation "11_alu_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "11_alu_shift_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-register operand
@ -91,7 +97,9 @@
;; the shift stage.
(define_insn_reservation "11_alu_shift_reg_op" 3
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg"))
"e_1*2,e_2,e_3,e_wb")
;; alu_ops can start sooner, if there is no shifter dependency

12
gcc/config/arm/arm926ejs.md
View File

@ -58,7 +58,13 @@
;; ALU operations with no shifted operand
(define_insn_reservation "9_alu_op" 1
(and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
shift_imm,shift_reg,extend,\
mov_imm,mov_reg,mov_shift,\
mvn_imm,mvn_reg,mvn_shift"))
"e,m,w")
@ -69,7 +75,9 @@
;; the execute stage.
(define_insn_reservation "9_alu_shift_reg_op" 2
(and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg"))
"e*2,m,w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

19
gcc/config/arm/cortex-a15.md
View File

@ -61,22 +61,31 @@
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg"))
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift"))
(eq_attr "type" "extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
mov_shift,mvn_shift"))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg"))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
|(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")

12
gcc/config/arm/cortex-a5.md
View File

@ -58,13 +58,21 @@
(define_insn_reservation "cortex_a5_alu" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
(eq_attr "type" "extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a5_ex1")

13
gcc/config/arm/cortex-a53.md
View File

@ -67,13 +67,20 @@
(define_insn_reservation "cortex_a53_alu" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,csel,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "arlo_shift,arlo_shift_reg,\
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a53_slot_any")
@ -202,7 +209,7 @@
(define_insn_reservation "cortex_a53_fpalu" 4
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
fcmps, fcmpd"))
fcmps, fcmpd, fcsel"))
"cortex_a53_slot0+cortex_a53_fpadd_pipe")
(define_insn_reservation "cortex_a53_fconst" 2

13
gcc/config/arm/cortex-a7.md
View File

@ -86,7 +86,8 @@
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
(ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm,extend")
(ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
mov_imm,mvn_imm,extend")
(and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
(not (eq_attr "length" "8")))))
"cortex_a7_ex2|cortex_a7_ex1")
@ -95,12 +96,18 @@
;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg"))
(eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
bfm,rev,\
shift_imm,shift_reg,mov_reg,mvn_reg"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "arlo_shift,arlo_shift_reg,\
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a7_ex1")

13
gcc/config/arm/cortex-a8.md
View File

@ -85,17 +85,24 @@
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz"))
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "extend,arlo_shift"))
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg"))
"cortex_a8_default")
;; Move instructions.

13
gcc/config/arm/cortex-a9.md
View File

@ -80,7 +80,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift"))
"cortex_a9_p0_default|cortex_a9_p1_default")
@ -88,8 +92,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
(eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\
mvn_shift,mvn_shift_reg"))
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
extend,mvn_shift,mvn_shift_reg"))
"cortex_a9_p0_shift | cortex_a9_p1_shift")
;; Loads have a latency of 4 cycles.

11
gcc/config/arm/cortex-m4.md
View File

@ -31,8 +31,15 @@
;; ALU and multiply is one cycle.
(define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4")
(ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
arlo_shift,arlo_shift_reg,\
(ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
(ior (eq_attr "mul32" "yes")

14
gcc/config/arm/cortex-r4.md
View File

@ -78,7 +78,11 @@
;; for the purposes of the dual-issue constraints above.
(define_insn_reservation "cortex_r4_alu" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,mvn_imm,mvn_reg"))
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,mvn_imm,mvn_reg"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_mov" 2
@ -88,12 +92,16 @@
(define_insn_reservation "cortex_r4_alu_shift" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_alu_shift_reg" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.

12
gcc/config/arm/fa526.md
View File

@ -62,13 +62,21 @@
;; ALU operations
(define_insn_reservation "526_alu_op" 1
(and (eq_attr "tune" "fa526")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
(and (eq_attr "tune" "fa526")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
(eq_attr "type" "extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fa526_core")

11
gcc/config/arm/fa606te.md
View File

@ -62,8 +62,15 @@
;; ALU operations
(define_insn_reservation "606te_alu_op" 1
(and (eq_attr "tune" "fa606te")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,
extend,arlo_shift,arlo_shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
"fa606te_core")

12
gcc/config/arm/fa626te.md
View File

@ -68,13 +68,21 @@
;; ALU operations
(define_insn_reservation "626te_alu_op" 1
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
(eq_attr "type" "extend,\
alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fa626te_core")

12
gcc/config/arm/fa726te.md
View File

@ -86,7 +86,11 @@
;; Other ALU instructions 2 cycles.
(define_insn_reservation "726te_alu_op" 1
(and (eq_attr "tune" "fa726te")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with a shift-by-register operand.
@ -95,12 +99,14 @@
;; it takes 3 cycles.
(define_insn_reservation "726te_alu_shift_op" 3
(and (eq_attr "tune" "fa726te")
(eq_attr "type" "extend,arlo_shift"))
(eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
(define_insn_reservation "726te_alu_shift_reg_op" 3
(and (eq_attr "tune" "fa726te")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Multiplication Instructions

10
gcc/config/arm/fmp626.md
View File

@ -63,13 +63,19 @@
;; ALU operations
(define_insn_reservation "mp626_alu_op" 1
(and (eq_attr "tune" "fmp626")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
(eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
logic_imm,logics_imm,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fmp626_core")
(define_insn_reservation "mp626_alu_shift_op" 2
(and (eq_attr "tune" "fmp626")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
(eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fmp626_core")

34
gcc/config/arm/marvell-pj4.md
View File

@ -53,26 +53,42 @@
(define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
logic_imm,logics_imm,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg")
(not (eq_attr "conds" "set")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
logic_imm,logics_imm,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg")
(eq_attr "conds" "set"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
(eq_attr "type" "alu_shift_imm,logic_shift_imm,\
alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,\
alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
(eq_attr "type" "alu_shift_imm,logic_shift_imm,\
alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,\
alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(eq_attr "conds" "set")
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
@ -80,14 +96,20 @@
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
(eq_attr "type" "alu_shift_imm,logic_shift_imm,\
alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,\
alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
(eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")

14
gcc/config/arm/thumb2.md
View File

@ -36,7 +36,7 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "arlo_shift")]
(set_attr "type" "alu_shift_imm")]
)
;; We use the '0' constraint for operand 1 because reload should
@ -282,7 +282,7 @@
ldr%?\\t%0, %1
str%?\\t%1, %0
str%?\\t%1, %0"
[(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1")
[(set_attr "type" "*,alu_imm,alu_imm,alu_imm,*,load1,load1,store1,store1")
(set_attr "length" "2,4,2,4,4,4,4,4,4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
@ -350,7 +350,7 @@
"cmn%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "arlo_shift")]
(set_attr "type" "alus_shift_imm")]
)
(define_insn_and_split "*thumb2_mov_scc"
@ -1102,8 +1102,8 @@
(set_attr "shift" "1")
(set_attr "length" "2")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
(const_string "alu_shift_imm")
(const_string "alu_shift_reg")))]
)
(define_insn "*thumb2_mov<mode>_shortim"
@ -1225,7 +1225,7 @@
"
[(set_attr "conds" "set")
(set_attr "length" "2,2,4,4")
(set_attr "type" "arlo_imm,*,arlo_imm,*")]
(set_attr "type" "alus_imm,alus_reg,alus_imm,alus_reg")]
)
(define_insn "*thumb2_mulsi_short"
@ -1351,7 +1351,7 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "arlo_shift")]
(set_attr "type" "alu_shift_imm")]
)
(define_peephole2

85
gcc/config/arm/types.md
View File

@ -23,21 +23,37 @@
;
; Instruction classification:
;
; arlo_imm any arithmetic or logical instruction that doesn't have
; a shifted operand and has an immediate operand. This
; adc_imm add/subtract with carry and with an immediate operand.
; adc_reg add/subtract with carry and no immediate operand.
; adcs_imm as adc_imm, setting condition flags.
; adcs_reg as adc_reg, setting condition flags.
; adr calculate address.
; alu_ext From ARMv8-A: any arithmetic instruction that has a
; sign/zero-extended.
; AArch64 Only.
; source operand
; alu_imm any arithmetic instruction that doesn't have a shifted
; operand and has an immediate operand. This
; excludes MOV, MVN and RSB(S) immediate.
; arlo_reg any arithmetic or logical instruction that doesn't have
; a shifted or an immediate operand. This excludes
; alu_reg any arithmetic instruction that doesn't have a shifted
; or an immediate operand. This excludes
; MOV and MVN but includes MOVT. This is also the default.
; arlo_shift any arithmetic or logical instruction that has a source
; operand shifted by a constant. This excludes
; simple shifts.
; arlo_shift_reg as arlo_shift, with the shift amount specified in a
; alu_shift_imm any arithmetic instruction that has a source operand
; shifted by a constant. This excludes simple shifts.
; alu_shift_reg as alu_shift_imm, with the shift amount specified in a
; register.
; alus_ext From ARMv8-A: as alu_ext, setting condition flags.
; AArch64 Only.
; alus_imm as alu_imm, setting condition flags.
; alus_reg as alu_reg, setting condition flags.
; alus_shift_imm as alu_shift_imm, setting condition flags.
; alus_shift_reg as alu_shift_reg, setting condition flags.
; bfm bitfield move operation.
; block blockage insn, this blocks all functional units.
; branch branch.
; call subroutine call.
; clz count leading zeros (CLZ).
; csel From ARMv8-A: conditional select.
; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
; f_cvt conversion between float and integral.
; f_flag transfer of co-processor flags to the CPSR.
@ -54,6 +70,7 @@
; fcmp[d,s] double/single floating-point compare.
; fconst[d,s] double/single load immediate.
; fcpys single precision floating point cpy.
; fcsel From ARMv8-A: Floating-point conditional select.
; fdiv[d,s] double/single precision floating point division.
; ffarith[d,s] double/single floating point abs/neg/cpy.
; ffma[d,s] double/single floating point fused multiply-accumulate.
@ -66,6 +83,18 @@
; load2 load 2 words from memory to arm registers.
; load3 load 3 words from memory to arm registers.
; load4 load 4 words from memory to arm registers.
; logic_imm any logical instruction that doesn't have a shifted
; operand and has an immediate operand.
; logic_reg any logical instruction that doesn't have a shifted
; operand or an immediate operand.
; logic_shift_imm any logical instruction that has a source operand
; shifted by a constant. This excludes simple shifts.
; logic_shift_reg as logic_shift_imm, with the shift amount specified in a
; register.
; logics_imm as logic_imm, setting condition flags.
; logics_reg as logic_reg, setting condition flags.
; logics_shift_imm as logic_shift_imm, setting condition flags.
; logics_shift_reg as logic_shift_reg, setting condition flags.
; mla integer multiply accumulate.
; mlas integer multiply accumulate, flag setting.
; mov_imm simple MOV instruction that moves an immediate to
@ -80,8 +109,10 @@
; mvn_reg inverting move instruction, register.
; mvn_shift inverting move instruction, shifted operand by a constant.
; mvn_shift_reg inverting move instruction, shifted operand by a register.
; rbit reverse bits.
; rev reverse bytes.
; sdiv signed division.
; shift simple shift operation (LSL, LSR, ASR, ROR) with an
; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an
; immediate.
; shift_reg simple shift by a register.
; smlad signed multiply accumulate dual.
@ -250,14 +281,27 @@
; neon_vst3_vst4
(define_attr "type"
"arlo_imm,\
arlo_reg,\
arlo_shift,\
arlo_shift_reg,\
"adc_imm,\
adc_reg,\
adcs_imm,\
adcs_reg,\
adr,\
alu_ext,\
alu_imm,\
alu_reg,\
alu_shift_imm,\
alu_shift_reg,\
alus_ext,\
alus_imm,\
alus_reg,\
alus_shift_imm,\
alus_shift_reg,\
bfm,\
block,\
branch,\
call,\
clz,\
csel,\
extend,\
f_cvt,\
f_flag,\
@ -282,6 +326,7 @@
fconstd,\
fconsts,\
fcpys,\
fcsel,\
fdivd,\
fdivs,\
ffarithd,\
@ -299,6 +344,14 @@
load2,\
load3,\
load4,\
logic_imm,\
logic_reg,\
logic_shift_imm,\
logic_shift_reg,\
logics_imm,\
logics_reg,\
logics_shift_imm,\
logics_shift_reg,\
mla,\
mlas,\
mov_imm,\
@ -311,8 +364,10 @@
mvn_reg,\
mvn_shift,\
mvn_shift_reg,\
rbit,\
rev,\
sdiv,\
shift,\
shift_imm,\
shift_reg,\
smlad,\
smladx,\
@ -469,7 +524,7 @@
neon_vst2_4_regs_vst3_vst4,\
neon_vst3_vst4_lane,\
neon_vst3_vst4"
(const_string "arlo_reg"))
(const_string "alu_imm"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"