re PR target/50447 ([avr] Better support of AND, OR, XOR and PLUS with constant integers for 16- and 32-bit values)
PR target/50447 PR target/50465 * config/avr/avr-protos.h (avr_out_bitop): New prototype. (avr_popcount_each_byte): New prototype. * config/avr/avr.c (avr_popcount): New static function. (avr_popcount_each_byte): New function. (avr_out_bitop): New function. (adjust_insn_length): ADJUST_LEN_OUT_BITOP dispatches to avr_out_bitop. Cleanup code. * config/avr/constraints.md (Ca2, Co2, Cx2): New constraints. (Ca4, Co4, Cx4): New constraints. * config/avr/avr.md (adjust_len): Add "out_bitop" insn attribute alternative. (andhi3, iorhi3, xorhi3): Rewrite insns using avr_out_bitop. (andsi3, iorsi3, xorsi3): Ditto. (*iorhi3_clobber, *iorsi3_clobber): Remove insns. From-SVN: r179081
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
58c1ae3667
commit
6ebe2d6cf6
@ -1,3 +1,22 @@
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2011-09-22 Georg-Johann Lay <avr@gjlay.de>
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PR target/50447
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PR target/50465
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* config/avr/avr-protos.h (avr_out_bitop): New prototype.
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(avr_popcount_each_byte): New prototype.
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* config/avr/avr.c (avr_popcount): New static function.
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(avr_popcount_each_byte): New function.
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(avr_out_bitop): New function.
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(adjust_insn_length): ADJUST_LEN_OUT_BITOP dispatches to
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avr_out_bitop. Cleanup code.
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* config/avr/constraints.md (Ca2, Co2, Cx2): New constraints.
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(Ca4, Co4, Cx4): New constraints.
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* config/avr/avr.md (adjust_len): Add "out_bitop" insn attribute
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alternative.
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(andhi3, iorhi3, xorhi3): Rewrite insns using avr_out_bitop.
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(andsi3, iorsi3, xorsi3): Ditto.
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(*iorhi3_clobber, *iorsi3_clobber): Remove insns.
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2011-09-22 Ira Rosen <ira.rosen@linaro.org>
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PR tree-optimization/50451
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@ -81,6 +81,8 @@ extern int avr_epilogue_uses (int regno);
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extern void avr_output_bld (rtx operands[], int bit_nr);
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extern void avr_output_addr_vec_elt (FILE *stream, int value);
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extern const char *avr_out_sbxx_branch (rtx insn, rtx operands[]);
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extern const char* avr_out_bitop (rtx, rtx*, int*);
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extern bool avr_popcount_each_byte (rtx, int, int);
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extern int extra_constraint_Q (rtx x);
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extern int adjust_insn_length (rtx insn, int len);
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@ -303,6 +303,46 @@ avr_replace_prefix (const char *old_str,
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return (const char*) new_str;
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}
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/* Custom function to count number of set bits. */
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static inline int
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avr_popcount (unsigned int val)
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{
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int pop = 0;
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while (val)
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{
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val &= val-1;
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pop++;
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}
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return pop;
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}
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/* Constraint helper function. XVAL is an CONST_INT. Return true if the least
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significant N_BYTES bytes of XVAL all have a popcount in POP_MASK and false,
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otherwise. POP_MASK represents a subset of integers which contains an
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integer N iff bit N of POP_MASK is set. */
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bool
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avr_popcount_each_byte (rtx xval, int n_bytes, int pop_mask)
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{
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int i;
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for (i = 0; i < n_bytes; i++)
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{
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rtx xval8 = simplify_gen_subreg (QImode, xval, SImode, i);
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unsigned int val8 = UINTVAL (xval8) & GET_MODE_MASK (QImode);
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if (0 == (pop_mask & (1 << avr_popcount (val8))))
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return false;
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}
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return true;
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}
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static void
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avr_option_override (void)
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{
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@ -4462,6 +4502,157 @@ lshrsi3_out (rtx insn, rtx operands[], int *len)
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return "";
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}
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/* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile
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time constant XOP[2]:
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XOP[0] = XOP[0] <op> XOP[2]
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and return "". If PLEN == NULL, print assembler instructions to perform the
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operation; otherwise, set *PLEN to the length of the instruction sequence
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(in words) printed with PLEN == NULL. XOP[3] is either an 8-bit clobber
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register or SCRATCH if no clobber register is needed for the operation. */
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const char*
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avr_out_bitop (rtx insn, rtx *xop, int *plen)
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{
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/* CODE and MODE of the operation. */
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enum rtx_code code = GET_CODE (SET_SRC (single_set (insn)));
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enum machine_mode mode = GET_MODE (xop[0]);
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/* Number of bytes to operate on. */
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int i, n_bytes = GET_MODE_SIZE (mode);
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/* Value of T-flag (0 or 1) or -1 if unknow. */
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int set_t = -1;
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/* Value (0..0xff) held in clobber register op[3] or -1 if unknown. */
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int clobber_val = -1;
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/* op[0]: 8-bit destination register
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op[1]: 8-bit const int
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op[2]: 8-bit clobber register or SCRATCH
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op[3]: 8-bit register containing 0xff or NULL_RTX */
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rtx op[4];
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op[2] = xop[3];
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op[3] = NULL_RTX;
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if (plen)
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*plen = 0;
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for (i = 0; i < n_bytes; i++)
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{
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/* We operate byte-wise on the destination. */
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rtx reg8 = simplify_gen_subreg (QImode, xop[0], mode, i);
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rtx xval8 = simplify_gen_subreg (QImode, xop[2], mode, i);
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/* 8-bit value to operate with this byte. */
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unsigned int val8 = UINTVAL (xval8) & GET_MODE_MASK (QImode);
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/* Number of bits set in the current byte of the constant. */
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int pop8 = avr_popcount (val8);
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/* Registers R16..R31 can operate with immediate. */
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bool ld_reg_p = test_hard_reg_class (LD_REGS, reg8);
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op[0] = reg8;
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op[1] = GEN_INT (val8);
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switch (code)
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{
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case IOR:
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if (0 == pop8)
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continue;
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else if (ld_reg_p)
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avr_asm_len ("ori %0,%1", op, plen, 1);
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else if (1 == pop8)
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{
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if (set_t != 1)
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avr_asm_len ("set", op, plen, 1);
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set_t = 1;
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op[1] = GEN_INT (exact_log2 (val8));
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avr_asm_len ("bld %0,%1", op, plen, 1);
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}
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else if (8 == pop8)
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{
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if (op[3] != NULL_RTX)
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avr_asm_len ("mov %0,%3", op, plen, 1);
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else
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avr_asm_len ("clr %0" CR_TAB
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"dec %0", op, plen, 2);
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op[3] = op[0];
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}
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else
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{
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if (clobber_val != (int) val8)
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avr_asm_len ("ldi %2,%1", op, plen, 1);
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clobber_val = (int) val8;
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avr_asm_len ("or %0,%2", op, plen, 1);
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}
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continue; /* IOR */
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case AND:
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if (8 == pop8)
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continue;
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else if (0 == pop8)
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avr_asm_len ("clr %0", op, plen, 1);
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else if (ld_reg_p)
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avr_asm_len ("andi %0,%1", op, plen, 1);
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else if (7 == pop8)
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{
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if (set_t != 0)
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avr_asm_len ("clt", op, plen, 1);
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set_t = 0;
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op[1] = GEN_INT (exact_log2 (GET_MODE_MASK (QImode) & ~val8));
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avr_asm_len ("bld %0,%1", op, plen, 1);
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}
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else
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{
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if (clobber_val != (int) val8)
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avr_asm_len ("ldi %2,%1", op, plen, 1);
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clobber_val = (int) val8;
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avr_asm_len ("and %0,%2", op, plen, 1);
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}
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continue; /* AND */
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case XOR:
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if (0 == pop8)
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continue;
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else if (8 == pop8)
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avr_asm_len ("com %0", op, plen, 1);
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else if (ld_reg_p && val8 == (1 << 7))
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avr_asm_len ("subi %0,%1", op, plen, 1);
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else
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{
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if (clobber_val != (int) val8)
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avr_asm_len ("ldi %2,%1", op, plen, 1);
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clobber_val = (int) val8;
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avr_asm_len ("eor %0,%2", op, plen, 1);
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}
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continue; /* XOR */
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default:
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/* Unknown rtx_code */
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gcc_unreachable();
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}
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} /* for all sub-bytes */
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return "";
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}
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/* Create RTL split patterns for byte sized rotate expressions. This
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produces a series of move instructions and considers overlap situations.
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Overlapping non-HImode operands need a scratch register. */
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@ -4656,6 +4847,10 @@ adjust_insn_length (rtx insn, int len)
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output_reload_insisf (insn, op, op[2], &len);
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break;
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case ADJUST_LEN_OUT_BITOP:
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avr_out_bitop (insn, op, &len);
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break;
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default:
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gcc_unreachable();
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}
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@ -4700,36 +4895,6 @@ adjust_insn_length (rtx insn, int len)
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default: break;
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}
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}
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else if (GET_CODE (op[1]) == AND)
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{
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if (GET_CODE (XEXP (op[1],1)) == CONST_INT)
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{
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HOST_WIDE_INT mask = INTVAL (XEXP (op[1],1));
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if (GET_MODE (op[1]) == SImode)
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len = (((mask & 0xff) != 0xff)
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+ ((mask & 0xff00) != 0xff00)
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+ ((mask & 0xff0000L) != 0xff0000L)
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+ ((mask & 0xff000000L) != 0xff000000L));
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else if (GET_MODE (op[1]) == HImode)
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len = (((mask & 0xff) != 0xff)
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+ ((mask & 0xff00) != 0xff00));
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}
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}
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else if (GET_CODE (op[1]) == IOR)
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{
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if (GET_CODE (XEXP (op[1],1)) == CONST_INT)
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{
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HOST_WIDE_INT mask = INTVAL (XEXP (op[1],1));
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if (GET_MODE (op[1]) == SImode)
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len = (((mask & 0xff) != 0)
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+ ((mask & 0xff00) != 0)
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+ ((mask & 0xff0000L) != 0)
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+ ((mask & 0xff000000L) != 0));
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else if (GET_MODE (op[1]) == HImode)
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len = (((mask & 0xff) != 0)
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+ ((mask & 0xff00) != 0));
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}
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}
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}
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set = single_set (insn);
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if (set)
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@ -136,7 +136,7 @@
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;; Otherwise do special processing depending on the attribute.
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(define_attr "adjust_len"
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"yes,no,reload_in32"
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"yes,no,reload_in32,out_bitop"
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(const_string "yes"))
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;; Define mode iterators
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@ -2238,71 +2238,41 @@
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(set_attr "cc" "set_zn,set_zn")])
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(define_insn "andhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,d,r")
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(and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
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(match_operand:HI 2 "nonmemory_operand" "r,i,M")))
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(clobber (match_scratch:QI 3 "=X,X,&d"))]
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[(set (match_operand:HI 0 "register_operand" "=r,d,d,r ,r")
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(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
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(match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
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""
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{
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if (which_alternative == 0)
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return ("and %A0,%A2" CR_TAB
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"and %B0,%B2");
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return "and %A0,%A2\;and %B0,%B2";
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else if (which_alternative == 1)
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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int mask = INTVAL (operands[2]);
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if ((mask & 0xff) != 0xff)
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output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
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if ((mask & 0xff00) != 0xff00)
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output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
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return "";
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return "andi %A0,lo8(%2)\;andi %B0,hi8(%2)";
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return avr_out_bitop (insn, operands, NULL);
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}
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return (AS2 (andi,%A0,lo8(%2)) CR_TAB
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AS2 (andi,%B0,hi8(%2)));
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}
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return (AS2 (ldi,%3,lo8(%2)) CR_TAB
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"and %A0,%3" CR_TAB
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AS1 (clr,%B0));
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}
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[(set_attr "length" "2,2,3")
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(set_attr "cc" "set_n,clobber,set_n")])
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[(set_attr "length" "2,2,2,4,4")
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(set_attr "adjust_len" "no,no,out_bitop,out_bitop,out_bitop")
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(set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(and:SI (match_operand:SI 1 "register_operand" "%0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,i")))]
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[(set (match_operand:SI 0 "register_operand" "=r,d,r ,r")
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(and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
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(match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
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(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
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""
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{
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if (which_alternative == 0)
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return ("and %0,%2" CR_TAB
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return "and %0,%2" CR_TAB
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"and %B0,%B2" CR_TAB
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"and %C0,%C2" CR_TAB
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"and %D0,%D2");
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else if (which_alternative==1)
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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HOST_WIDE_INT mask = INTVAL (operands[2]);
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if ((mask & 0xff) != 0xff)
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output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
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if ((mask & 0xff00) != 0xff00)
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output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
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if ((mask & 0xff0000L) != 0xff0000L)
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output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
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if ((mask & 0xff000000L) != 0xff000000L)
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output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
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return "";
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"and %D0,%D2";
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return avr_out_bitop (insn, operands, NULL);
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}
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return (AS2 (andi, %A0,lo8(%2)) CR_TAB
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AS2 (andi, %B0,hi8(%2)) CR_TAB
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AS2 (andi, %C0,hlo8(%2)) CR_TAB
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AS2 (andi, %D0,hhi8(%2)));
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}
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return "bug";
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}
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[(set_attr "length" "4,4")
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(set_attr "cc" "set_n,clobber")])
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[(set_attr "length" "4,4,8,8")
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(set_attr "adjust_len" "no,out_bitop,out_bitop,out_bitop")
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(set_attr "cc" "set_n,clobber,clobber,clobber")])
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(define_peephole2 ; andi
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[(set (match_operand:QI 0 "d_register_operand" "")
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@ -2332,84 +2302,41 @@
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(set_attr "cc" "set_zn,set_zn")])
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(define_insn "iorhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,d")
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(ior:HI (match_operand:HI 1 "register_operand" "%0,0")
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(match_operand:HI 2 "nonmemory_operand" "r,i")))]
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[(set (match_operand:HI 0 "register_operand" "=r,d,d,r ,r")
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(ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
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(match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
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""
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{
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if (which_alternative == 0)
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return ("or %A0,%A2" CR_TAB
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"or %B0,%B2");
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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int mask = INTVAL (operands[2]);
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if (mask & 0xff)
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output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
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if (mask & 0xff00)
|
||||
output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
|
||||
return "";
|
||||
}
|
||||
return (AS2 (ori,%0,lo8(%2)) CR_TAB
|
||||
AS2 (ori,%B0,hi8(%2)));
|
||||
}
|
||||
[(set_attr "length" "2,2")
|
||||
(set_attr "cc" "set_n,clobber")])
|
||||
return "or %A0,%A2\;or %B0,%B2";
|
||||
else if (which_alternative == 1)
|
||||
return "ori %A0,lo8(%2)\;ori %B0,hi8(%2)";
|
||||
|
||||
(define_insn "*iorhi3_clobber"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
||||
(ior:HI (match_operand:HI 1 "register_operand" "%0,0")
|
||||
(match_operand:HI 2 "immediate_operand" "M,i")))
|
||||
(clobber (match_scratch:QI 3 "=&d,&d"))]
|
||||
""
|
||||
"@
|
||||
ldi %3,lo8(%2)\;or %A0,%3
|
||||
ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "clobber,set_n")])
|
||||
return avr_out_bitop (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "length" "2,2,2,4,4")
|
||||
(set_attr "adjust_len" "no,no,out_bitop,out_bitop,out_bitop")
|
||||
(set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
|
||||
|
||||
(define_insn "iorsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,d")
|
||||
(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "r,i")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,d,r ,r")
|
||||
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
|
||||
""
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return ("or %0,%2" CR_TAB
|
||||
return "or %0,%2" CR_TAB
|
||||
"or %B0,%B2" CR_TAB
|
||||
"or %C0,%C2" CR_TAB
|
||||
"or %D0,%D2");
|
||||
if (GET_CODE (operands[2]) == CONST_INT)
|
||||
{
|
||||
HOST_WIDE_INT mask = INTVAL (operands[2]);
|
||||
if (mask & 0xff)
|
||||
output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
|
||||
if (mask & 0xff00)
|
||||
output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
|
||||
if (mask & 0xff0000L)
|
||||
output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
|
||||
if (mask & 0xff000000L)
|
||||
output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
|
||||
return "";
|
||||
}
|
||||
return (AS2 (ori, %A0,lo8(%2)) CR_TAB
|
||||
AS2 (ori, %B0,hi8(%2)) CR_TAB
|
||||
AS2 (ori, %C0,hlo8(%2)) CR_TAB
|
||||
AS2 (ori, %D0,hhi8(%2)));
|
||||
}
|
||||
[(set_attr "length" "4,4")
|
||||
(set_attr "cc" "set_n,clobber")])
|
||||
"or %D0,%D2";
|
||||
|
||||
(define_insn "*iorsi3_clobber"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
|
||||
(match_operand:SI 2 "immediate_operand" "M,i")))
|
||||
(clobber (match_scratch:QI 3 "=&d,&d"))]
|
||||
""
|
||||
"@
|
||||
ldi %3,lo8(%2)\;or %A0,%3
|
||||
ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
|
||||
[(set_attr "length" "2,8")
|
||||
(set_attr "cc" "clobber,set_n")])
|
||||
return avr_out_bitop (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "length" "4,4,8,8")
|
||||
(set_attr "adjust_len" "no,out_bitop,out_bitop,out_bitop")
|
||||
(set_attr "cc" "set_n,clobber,clobber,clobber")])
|
||||
|
||||
;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
;; xor
|
||||
@ -2424,26 +2351,39 @@
|
||||
(set_attr "cc" "set_zn")])
|
||||
|
||||
(define_insn "xorhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(xor:HI (match_operand:HI 1 "register_operand" "%0")
|
||||
(match_operand:HI 2 "register_operand" "r")))]
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r ,r")
|
||||
(xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
|
||||
(match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
|
||||
""
|
||||
"eor %0,%2
|
||||
eor %B0,%B2"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_n")])
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return "eor %A0,%A2\;eor %B0,%B2";
|
||||
|
||||
return avr_out_bitop (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "length" "2,2,4")
|
||||
(set_attr "adjust_len" "no,out_bitop,out_bitop")
|
||||
(set_attr "cc" "set_n,clobber,clobber")])
|
||||
|
||||
(define_insn "xorsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(xor:SI (match_operand:SI 1 "register_operand" "%0")
|
||||
(match_operand:SI 2 "register_operand" "r")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r ,r")
|
||||
(xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
|
||||
""
|
||||
"eor %0,%2
|
||||
eor %B0,%B2
|
||||
eor %C0,%C2
|
||||
eor %D0,%D2"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "set_n")])
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return "eor %0,%2" CR_TAB
|
||||
"eor %B0,%B2" CR_TAB
|
||||
"eor %C0,%C2" CR_TAB
|
||||
"eor %D0,%D2";
|
||||
|
||||
return avr_out_bitop (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "length" "4,8,8")
|
||||
(set_attr "adjust_len" "no,out_bitop,out_bitop")
|
||||
(set_attr "cc" "set_n,clobber,clobber")])
|
||||
|
||||
;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
|
||||
;; swap
|
||||
|
||||
@ -112,3 +112,33 @@
|
||||
"Constant integer 4."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival == 4")))
|
||||
|
||||
(define_constraint "Ca2"
|
||||
"Constant 2-byte integer that allows AND without clobber register."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_popcount_each_byte (op, 2, (1<<0) | (1<<7) | (1<<8))")))
|
||||
|
||||
(define_constraint "Ca4"
|
||||
"Constant 4-byte integer that allows AND without clobber register."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_popcount_each_byte (op, 4, (1<<0) | (1<<7) | (1<<8))")))
|
||||
|
||||
(define_constraint "Co2"
|
||||
"Constant 2-byte integer that allows OR without clobber register."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_popcount_each_byte (op, 2, (1<<0) | (1<<1) | (1<<8))")))
|
||||
|
||||
(define_constraint "Co4"
|
||||
"Constant 4-byte integer that allows OR without clobber register."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_popcount_each_byte (op, 4, (1<<0) | (1<<1) | (1<<8))")))
|
||||
|
||||
(define_constraint "Cx2"
|
||||
"Constant 2-byte integer that allows XOR without clobber register."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_popcount_each_byte (op, 2, (1<<0) | (1<<8))")))
|
||||
|
||||
(define_constraint "Cx4"
|
||||
"Constant 4-byte integer that allows XOR without clobber register."
|
||||
(and (match_code "const_int")
|
||||
(match_test "avr_popcount_each_byte (op, 4, (1<<0) | (1<<8))")))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user