re PR target/35768 (gcc.c-torture/compile/20010226-1.c:22: ICE: in do_output_reload, at reload1.c:7331)
PR target/35768 * pa.md: Define mode iterator P. Define mode attribute dwc. (dcacheflush): Update pattern to use iterator P and attribute dwc. (icacheflush): Likewise. * pa.h (INITIALIZE_TRAMPOLINE): Use dcacheflushsi/icacheflushsi if !TARGET_64BIT, and dcacheflushdi/icacheflushdi if TARGET_64BIT. From-SVN: r134182
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John David Anglin
John David Anglin
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6ef5fab099
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@ -1,3 +1,12 @@
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2008-04-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR target/35768
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* pa.md: Define mode iterator P. Define mode attribute dwc.
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(dcacheflush): Update pattern to use iterator P and attribute dwc.
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(icacheflush): Likewise.
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* pa.h (INITIALIZE_TRAMPOLINE): Use dcacheflushsi/icacheflushsi if
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!TARGET_64BIT, and dcacheflushdi/icacheflushdi if TARGET_64BIT.
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2008-04-11 Ben Elliston <bje@au.ibm.com>
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* config/spu/spu.c (spu_init_builtins): Mark builtins as nothrow.
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@ -1,6 +1,6 @@
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/* Definitions of target machine for GNU compiler, for the HP Spectrum.
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Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
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Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
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2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
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and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
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Software Science at the University of Utah.
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@ -921,8 +921,8 @@ extern int may_call_alloca;
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emit_insn (gen_andsi3 (end_addr, tmp, \
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GEN_INT (-MIN_CACHELINE_SIZE))); \
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emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
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emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
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emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
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emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));\
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emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length, \
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gen_reg_rtx (Pmode), \
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gen_reg_rtx (Pmode))); \
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} \
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@ -953,8 +953,8 @@ extern int may_call_alloca;
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emit_insn (gen_anddi3 (end_addr, tmp, \
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GEN_INT (-MIN_CACHELINE_SIZE))); \
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emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
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emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
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emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
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emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));\
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emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length, \
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gen_reg_rtx (Pmode), \
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gen_reg_rtx (Pmode))); \
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} \
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@ -1,6 +1,6 @@
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;;- Machine description for HP PA-RISC architecture for GCC compiler
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;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
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;; 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
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;; 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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;; Contributed by the Center for Software Science at the University
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;; of Utah.
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@ -64,6 +64,16 @@
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(MAX_17BIT_OFFSET 262100) ; 17-bit branch
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])
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;; Mode and code iterators
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;; This mode iterator allows :P to be used for patterns that operate on
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;; pointer-sized quantities. Exactly one of the two alternatives will match.
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(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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;; This attribute defines the condition prefix for word and double word
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;; add, compare, subtract and logical instructions.
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(define_mode_attr dwc [(SI "") (DI "*")])
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;; Insn type. Used to default other attribute values.
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;; type "unary" insns have one input operand (1) and one output operand (0)
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@ -9610,42 +9620,34 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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[(set_attr "type" "fpalu")
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(set_attr "length" "4")])
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;; Flush the I and D cache lines from the start address (operand0)
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;; to the end address (operand1). No lines are flushed if the end
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;; address is less than the start address (unsigned).
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;; The following two patterns are used by the trampoline code for nested
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;; functions. They flush the I and D cache lines from the start address
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;; (operand0) to the end address (operand1). No lines are flushed if the
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;; end address is less than the start address (unsigned).
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;;
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;; Because the range of memory flushed is variable and the size of
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;; a MEM can only be a CONST_INT, the patterns specify that they
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;; perform an unspecified volatile operation on all memory.
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;; Because the range of memory flushed is variable and the size of a MEM
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;; can only be a CONST_INT, the patterns specify that they perform an
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;; unspecified volatile operation on all memory.
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;;
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;; The address range for an icache flush must lie within a single
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;; space on targets with non-equivalent space registers.
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;;
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;; This is used by the trampoline code for nested functions.
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;;
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;; Operand 0 contains the start address.
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;; Operand 1 contains the end address.
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;; Operand 2 contains the line length to use.
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;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
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(define_insn "dcacheflush"
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(define_insn "dcacheflush<P:mode>"
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[(const_int 1)
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(unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
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(use (match_operand 0 "pmode_register_operand" "r"))
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(use (match_operand 1 "pmode_register_operand" "r"))
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(use (match_operand 2 "pmode_register_operand" "r"))
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(clobber (match_scratch 3 "=&0"))]
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(clobber (match_scratch:P 3 "=&0"))]
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""
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"*
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{
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if (TARGET_64BIT)
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return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
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else
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return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
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}"
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"cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
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[(set_attr "type" "multi")
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(set_attr "length" "12")])
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(define_insn "icacheflush"
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(define_insn "icacheflush<P:mode>"
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[(const_int 2)
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(unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
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(use (match_operand 0 "pmode_register_operand" "r"))
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@ -9653,15 +9655,9 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(use (match_operand 2 "pmode_register_operand" "r"))
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(clobber (match_operand 3 "pmode_register_operand" "=&r"))
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(clobber (match_operand 4 "pmode_register_operand" "=&r"))
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(clobber (match_scratch 5 "=&0"))]
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(clobber (match_scratch:P 5 "=&0"))]
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""
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"*
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{
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if (TARGET_64BIT)
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return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
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else
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return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
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}"
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"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
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[(set_attr "type" "multi")
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(set_attr "length" "52")])
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