[ARM] Cleanup multiply patterns
Cleanup the 32-bit multiply patterns. Merge the pre-Armv6 with the Armv6 patterns, remove useless alternatives and order the accumulator operands to prefer MLA Ra, Rb, Rc, Ra whenever feasible. gcc/ * config/arm/arm.md (arm_mulsi3): Remove pattern. (arm_mulsi3_v6): Likewise. (mulsi3addsi_v6): Likewise. (mulsi3subsi): Likewise. (mul): Add new multiply pattern. (mla): Likewise. (mls): Likewise. From-SVN: r275897
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2019-09-18 Wilco Dijkstra <wdijkstr@arm.com>
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* config/arm/arm.md (arm_mulsi3): Remove pattern.
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(arm_mulsi3_v6): Likewise.
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(mulsi3addsi_v6): Likewise.
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(mulsi3subsi): Likewise.
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(mul): Add new multiply pattern.
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(mla): Likewise.
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(mls): Likewise.
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2019-09-18 Richard Biener <rguenther@suse.de>
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* tree-parloops.c (report_ploop_op): Copy from report_vect_op.
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@ -1595,28 +1595,46 @@
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""
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)
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;; Use `&' and then `0' to prevent the operands 0 and 1 being the same
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(define_insn "*arm_mulsi3"
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[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
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(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 1 "s_register_operand" "%0,r")))]
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"TARGET_32BIT && !arm_arch6"
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;; Use `&' and then `0' to prevent operands 0 and 2 being the same
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(define_insn "*mul"
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[(set (match_operand:SI 0 "s_register_operand" "=l,r,&r,&r")
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(mult:SI (match_operand:SI 2 "s_register_operand" "l,r,r,r")
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(match_operand:SI 1 "s_register_operand" "%0,r,0,r")))]
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"TARGET_32BIT"
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"mul%?\\t%0, %2, %1"
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[(set_attr "type" "mul")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "arch" "t2,v6,nov6,nov6")
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(set_attr "length" "4")
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(set_attr "predicable_short_it" "yes,no,*,*")]
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)
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(define_insn "*arm_mulsi3_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
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(mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r")
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(match_operand:SI 2 "s_register_operand" "l,0,r")))]
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"TARGET_32BIT && arm_arch6"
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"mul%?\\t%0, %1, %2"
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[(set_attr "type" "mul")
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;; MLA and MLS instruction. Use operand 1 for the accumulator to prefer
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;; reusing the same register.
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(define_insn "*mla"
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[(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r")
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(plus:SI
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(mult:SI (match_operand:SI 3 "s_register_operand" "r,r,r,r")
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(match_operand:SI 2 "s_register_operand" "%r,r,0,r"))
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(match_operand:SI 1 "s_register_operand" "r,0,r,r")))]
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"TARGET_32BIT"
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"mla%?\\t%0, %3, %2, %1"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")
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(set_attr "arch" "t2,t2,*")
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(set_attr "length" "4")
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(set_attr "predicable_short_it" "yes,yes,no")]
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(set_attr "arch" "v6,nov6,nov6,nov6")]
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)
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(define_insn "*mls"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI
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(match_operand:SI 1 "s_register_operand" "r")
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(mult:SI (match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r"))))]
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"TARGET_32BIT && arm_arch_thumb2"
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"mls%?\\t%0, %3, %2, %1"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*mulsi3_compare0"
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@ -1673,32 +1691,6 @@
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(set_attr "type" "muls")]
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)
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;; Unnamed templates to match MLA instruction.
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(define_insn "*mulsi3addsi"
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[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
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(plus:SI
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(mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
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(match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
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(match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
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"TARGET_32BIT && !arm_arch6"
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"mla%?\\t%0, %2, %1, %3"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*mulsi3addsi_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI
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(mult:SI (match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))
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(match_operand:SI 3 "s_register_operand" "r")))]
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"TARGET_32BIT && arm_arch6"
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"mla%?\\t%0, %2, %1, %3"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*mulsi3addsi_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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@ -1763,18 +1755,6 @@
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(set_attr "type" "mlas")]
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)
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(define_insn "*mulsi3subsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI
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(match_operand:SI 3 "s_register_operand" "r")
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(mult:SI (match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))))]
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"TARGET_32BIT && arm_arch_thumb2"
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"mls%?\\t%0, %2, %1, %3"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")]
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)
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(define_expand "maddsidi4"
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[(set (match_operand:DI 0 "s_register_operand")
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(plus:DI
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