darwin-tramp.asm: Fix comment formatting.
* config/rs6000/darwin-tramp.asm: Fix comment formatting. * config/rs6000/freebsd.h: Likewise. * config/rs6000/rs6000.c: Likewise. * config/sh/sh.c: Likewise. * config/sh/sh.h: Likewise. From-SVN: r48362
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
fac510512c
commit
6f317ef34f
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@ -1,3 +1,11 @@
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2001-12-29 Kazu Hirata <kazu@hxi.com>
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* config/rs6000/darwin-tramp.asm: Fix comment formatting.
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* config/rs6000/freebsd.h: Likewise.
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* config/rs6000/rs6000.c: Likewise.
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* config/sh/sh.c: Likewise.
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* config/sh/sh.h: Likewise.
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2001-12-28 Stan Shebs <shebs@apple.com>
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* objc/objc-act.c (build_module_descriptor): Make sure the init
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@ -33,7 +33,7 @@
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* executable file might be covered by the GNU General Public License.
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*/
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/* Set up trampolines. */
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/* Set up trampolines. */
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.text
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.align 2
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@ -18,7 +18,7 @@ You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Override the defaults, which exist to force the proper definition. */
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/* Override the defaults, which exist to force the proper definition. */
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#undef CPP_OS_DEFAULT_SPEC
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#define CPP_OS_DEFAULT_SPEC "%(cpp_os_freebsd)"
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@ -722,7 +722,7 @@ xer_operand (op, mode)
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}
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/* Return 1 if OP is a signed 8-bit constant. Int multiplication
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by such constants completes more quickly. */
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by such constants completes more quickly. */
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int
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s8bit_cint_operand (op, mode)
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@ -1813,7 +1813,7 @@ rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
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&& GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
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{
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/* Result of previous invocation of this function on Darwin
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floating point constant. */
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floating point constant. */
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push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
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BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
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opnum, (enum reload_type)type);
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@ -3982,7 +3982,7 @@ altivec_init_builtins (void)
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def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
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def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
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/* Add the simple ternary operators. */
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/* Add the simple ternary operators. */
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d = (struct builtin_description *) bdesc_3arg;
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for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++)
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{
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@ -4280,7 +4280,7 @@ expand_block_move (operands)
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return 1;
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/* store_one_arg depends on expand_block_move to handle at least the size of
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reg_parm_stack_space. */
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reg_parm_stack_space. */
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if (bytes > (TARGET_POWERPC64 ? 64 : 32))
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return 0;
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@ -80,7 +80,7 @@ int pragma_nosave_low_regs;
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sh_expand_prologue. */
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int current_function_anonymous_args;
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/* Global variables for machine-dependent things. */
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/* Global variables for machine-dependent things. */
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/* Which cpu are we scheduling for. */
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enum processor_type sh_cpu;
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@ -1455,7 +1455,7 @@ shl_and_kind (left_rtx, mask_rtx, attrp)
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continue;
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}
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/* ??? Could try to put zero extend into initial right shift,
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or even shift a bit left before the right shift. */
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or even shift a bit left before the right shift. */
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/* Determine value of first part of left shift, to get to the
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zero extend cut-off point. */
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first = width - exact_log2 (lsb2) + right;
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@ -3236,7 +3236,7 @@ machine_dependent_reorg (first)
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entirely reliable around libcalls;
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newlib/libm/math/e_pow.c is a test case. Sometimes
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an insn will appear in LOG_LINKS even though it is
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not the most recent insn which sets the register. */
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not the most recent insn which sets the register. */
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if (foundinsn
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&& (scanset
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@ -3846,7 +3846,7 @@ output_stack_adjust (size, reg, temp)
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emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
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/* Try to do it with two partial adjustments; however, we must make
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sure that the stack is properly aligned at all times, in case
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an interrupt occurs between the two partial adjustments. */
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an interrupt occurs between the two partial adjustments. */
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else if (CONST_OK_FOR_I (size / 2 & -4)
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&& CONST_OK_FOR_I (size - (size / 2 & -4)))
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{
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@ -4082,7 +4082,7 @@ sh_expand_prologue ()
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extra_push = 0;
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/* This is set by SETUP_VARARGS to indicate that this is a varargs
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routine. Clear it here so that the next function isn't affected. */
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routine. Clear it here so that the next function isn't affected. */
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if (current_function_anonymous_args)
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{
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current_function_anonymous_args = 0;
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@ -4268,7 +4268,7 @@ sh_builtin_saveregs ()
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int bufsize, regno;
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HOST_WIDE_INT alias_set;
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/* Allocate block of memory for the regs. */
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/* Allocate block of memory for the regs. */
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/* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
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Or can assign_stack_local accept a 0 SIZE argument? */
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bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
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@ -5509,7 +5509,7 @@ nonpic_symbol_mentioned_p (x)
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}
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/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
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@GOTOFF in `reg'. */
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@GOTOFF in `reg'. */
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rtx
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legitimize_pic_address (orig, mode, reg)
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rtx orig;
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@ -164,10 +164,10 @@ extern int target_flags;
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/* Nonzero if we should generate code using type 3E insns. */
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#define TARGET_SH3E (target_flags & SH3E_BIT)
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/* Nonzero if the cache line size is 32. */
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/* Nonzero if the cache line size is 32. */
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#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
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/* Nonzero if we schedule for a superscalar implementation. */
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/* Nonzero if we schedule for a superscalar implementation. */
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#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
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/* Nonzero if the target has separate instruction and data caches. */
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@ -430,7 +430,7 @@ do { \
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&& GET_CODE (PREV_INSN (A_LABEL)) == INSN \
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&& GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
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&& XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
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/* explicit alignment insn in constant tables. */ \
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/* explicit alignment insn in constant tables. */ \
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? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
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: 0)
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@ -998,7 +998,7 @@ extern const enum reg_class reg_class_from_letter[];
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((TYPE) != 0 \
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&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
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|| TREE_ADDRESSABLE (TYPE)))
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/* Some subroutine macros specific to this machine. */
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/* Some subroutine macros specific to this machine. */
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#define BASE_RETURN_VALUE_REG(MODE) \
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((TARGET_SH3E && ((MODE) == SFmode)) \
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@ -1046,7 +1046,7 @@ extern const enum reg_class reg_class_from_letter[];
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#define LIBCALL_VALUE(MODE) \
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gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
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/* 1 if N is a possible register number for a function value. */
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/* 1 if N is a possible register number for a function value. */
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#define FUNCTION_VALUE_REGNO_P(REGNO) \
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((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
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@ -1134,7 +1134,7 @@ struct sh_args {
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: ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
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/* Return boolean indicating arg of mode MODE will be passed in a reg.
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This macro is only used in this file. */
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This macro is only used in this file. */
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#define PASS_IN_REG_P(CUM, MODE, TYPE) \
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(((TYPE) == 0 \
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@ -1642,7 +1642,7 @@ extern int current_function_anonymous_args;
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/* Define as C expression which evaluates to nonzero if the tablejump
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instruction expects the table to contain offsets from the address of the
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table.
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Do not define this if the table should contain absolute addresses. */
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Do not define this if the table should contain absolute addresses. */
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#define CASE_VECTOR_PC_RELATIVE 1
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/* Specify the tree operation to be used to convert reals to integers. */
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@ -1916,7 +1916,7 @@ while (0)
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specified as the number of bits.
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Try to use function `asm_output_aligned_bss' defined in file
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`varasm.c' when defining this macro. */
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`varasm.c' when defining this macro. */
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#ifndef ASM_OUTPUT_ALIGNED_BSS
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#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
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asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
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@ -2021,11 +2021,11 @@ extern char fp_reg_names[][5];
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assemble_name ((STREAM), (NAME)), \
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fputc ('\n', (STREAM)))
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/* The prefix to add to user-visible assembler symbols. */
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/* The prefix to add to user-visible assembler symbols. */
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#define USER_LABEL_PREFIX "_"
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/* The prefix to add to an internally generated label. */
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/* The prefix to add to an internally generated label. */
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#define LOCAL_LABEL_PREFIX ""
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